US2016225425A1PendingUtilityA1

Electronic devices having semiconductor memory units having magnetic tunnel junction element

Assignee: SK HYNIX INCPriority: Apr 9, 2013Filed: Apr 11, 2016Published: Aug 4, 2016
Est. expiryApr 9, 2033(~6.7 yrs left)· nominal 20-yr term from priority
G11C 11/161H01L 43/02H01L 43/10H10N 50/85H10B 61/00G11C 11/15H10N 50/10H10N 50/01H10B 61/22H10N 50/80G11C 11/1659
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Claims

Abstract

Disclosed are electronic devices comprising a semiconductor memory unit capable of reducing the switching current of a variable resistance element for switching between different resistance states. One implementation of a disclosed electronic device may include a first magnetic layer having an easy magnetization axis in a first direction and having a variable magnetization direction, a third magnetic layer having a magnetization direction pinned in the first direction, a second magnetic layer interposed between the first magnetic layer and the third magnetic layer, and having a magnetization direction pinned in a second direction different from the first direction, a tunnel barrier layer interposed between the first magnetic layer and the second magnetic layer, and a non-magnetic layer interposed between the second magnetic layer and the third magnetic layer.

Claims

exact text as granted — not AI-modified
1 - 16 . (canceled) 
     
     
         17 . An electronic device comprising a semiconductor memory unit that includes:
 a magnetization free layer having a variable magnetization direction and an easy magnetization axis in a first direction;   a magnetization pinned layer having a magnetization that is pinned in the first direction; and   a reference layer between the magnetization free layer and the magnetization pinned layer and having a magnetization angle inclined from an initial direction due to a magnetic exchange coupling between the reference layer and the magnetization pinned layer.   
     
     
         18 . The electronic device of  claim 17 , further comprising:
 a tunnel barrier layer between the magnetization free layer and the reference layer; and   a non-magnetic layer between the reference layer and the magnetization pinned layer to enable the magnetic exchange coupling between the reference layer and the magnetization pinned layer.   
     
     
         19 . The electronic device of  claim 17 , wherein:
 the reference layer and the magnetization pinned layer are ferromagnetically coupled.   
     
     
         20 . The electronic device of  claim 17 , wherein the reference layer and the magnetization pinned layer are anti-ferromagnetically coupled. 
     
     
         21 . The electronic device of  claim 20 , wherein the reference layer and the magnetization pinned layer are anti-ferromagnetically coupled when the magnetization direction of the reference layer is inclined toward a direction to the magnetization direction of the third magnetic layer. 
     
     
         22 . The electronic device of  claim 17 , wherein the reference layer has a magnetization direction pinned in a second direction which is vertically inclined from a surface of the reference layer 
     
     
         23 . The electronic device according to  claim 17 , wherein the magnetization free layer is magnetized parallel or anti-parallel to the magnetization direction of the magnetization pinned layer when the magnetization direction of the reference layer is inclined toward a direction opposite to the magnetization direction of the magnetization pinned layer. 
     
     
         24 . The electronic device according to  claim 17 , wherein the first direction is parallel to a surface of the magnetization free layer. 
     
     
         25 . The electronic device according to  claim 17 , wherein the second direction is inclined from the first direction at an angle of greater than 0 degree and less than 90 degrees. 
     
     
         26 . The electronic device according to  claim 25 , wherein the second direction is inclined from a direction vertical to a surface of the layer to a direction parallel to the surface of the layer. 
     
     
         27 . The electronic device according to  claim 17 , wherein the second direction is inclined from the first direction at an angle of greater than 90 degrees and less than 180. 
     
     
         28 . The electronic device according to  claim 17 , wherein the second direction is inclined from the first direction at an angle of greater than 180 degrees and less than 270 degrees. 
     
     
         29 . The electronic device according to  claim 17 , wherein the second direction is inclined from the first direction at an angle of greater than 270 degrees and less than 360 degrees. 
     
     
         30 . The electronic device according to  claim 17 , further comprising an anti-ferromagnetic layer that contacts with the magnetization pinned layer. 
     
     
         31 . The electronic device according to  claim 17 , wherein the magnetization free layer comprises a lower magnetic layer, an upper magnetic layer, and a non-magnetic layer interposed between the lower magnetic layer and the upper magnetic layer. 
     
     
         32 . The electronic device according to  claim 17 , further comprising:
 a first conductive layer coupled with the magnetization free layer, and   a second conductive layer coupled with the magnetization pinned layer.   
     
     
         33 . The electronic device according to  claim 32 , wherein:
 the first conductive layer is a seed layer, and   the second conductive layer is a capping layer.   
     
     
         34 . The electronic device according to  claim 17 , further comprising a microprocessor which includes:
 a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor;   an operation unit configured to perform an operation based on a result that the control unit decodes the command; and   a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed,   wherein the semiconductor memory unit is a part of the memory unit in the microprocessor.

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