Memory device for reducing a write fail, a system including the same, and a method thereof

Abstract

A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to continuously perform a plurality of write commands on the memory device between an active command and a precharge command. In the memory system, when after a first write operation having a last write command of the plurality of write commands is performed and then the precharge command is issued, the last write command is issued for a second write operation after the precharge command. The first write operation and the second write operation write a same data to memory cells of plurality of memory cells having a same address.

What is claimed is: 
     
         1 . A method of writing data to a memory device, the method comprising:
 receiving a plurality of write requests and a plurality of data sets from a host;   generating a plurality of write commands and storing the plurality of write commands to a write queue;   applying the plurality of write commands to a memory device between an active command and a precharge command based on a predetermined scheduling method; and   applying a last write command of the plurality of write commands to the memory device after the precharge command is performed.   
     
     
         2 . The method of  claim 1 , further comprising:
 executing at least one read command or at least one write command after applying the precharge command and before applying the last write command.   
     
     
         3 . The method of  claim 2 ,
 wherein the predetermined scheduling method determines a priority among the plurality of write commands based on a bank address and a row address.   
     
     
         4 . The method of  claim 1 , further comprising:
 removing a write command executed from the plurality of write command stored in the write queue,   wherein the last write command is retained after the precharge command and is executed after the precharge command.   
     
     
         5 . A memory controller, comprising:
 an arbiter configured to generate an active command, a precharge command, and a plurality of write commands and configured to issue the plurality of write commands between the active command and the precharge command,   wherein the precharge command is issued after a first write operation is performed in response to a last write command of the plurality of write commands , the last write command is issued for a second write operation after the precharge command, and   wherein the first write operation and the second write operation write a same data set to memory cells of plurality of memory cells.   
     
     
         6 . The memory controller of  claim 5 , further comprising:
 a write queue configured to store the plurality of write commands.   
     
     
         7 . The memory controller of  claim 5 ,
 wherein the data set include a number of data corresponding to a burst length.   
     
     
         8 . The memory system of  claim 6 ,
 wherein the arbiter further configured to:
 receive a plurality of write requests from a host; 
 generate the active command, the plurality of write commands, and the precharge command; 
 store the plurality of write commands in the write queue; and 
 schedule the commands stored in the write queue according to a predetermined scheduling algorithm.