Capped contact structure with variable adhesion layer thickness

Abstract

Metal oxide based memory devices and methods for manufacturing are described herein. A method for manufacturing a memory cell includes forming a bottom adhesion layer in a via formed in an insulating layer. Forming a bottom conductive plug in the bottom adhesion layer. Forming a top adhesion layer over the bottom adhesion layer and bottom conductive plug. Forming a top conductive plug in the top adhesion layer. Wherein the thickness of the bottom and top adhesion layers may be different from one another.

What is claimed is: 
     
         1 . A memory device comprising:
 a top electrode;   a metal oxide layer contacting the top electrode;   an interlayer conductor having an electrode surface contacting the metal oxide layer;   wherein the interlayer conductor comprises an upper portion including the electrode surface and a lower portion;   wherein the lower portion comprising a first conductive liner and a first conductive plug in the first conductive liner and the upper portion comprising a second conductive liner and a second conductive plug in the second conductive liner; and   wherein the second conductive liner includes sidewall portions having a thickness different than a thickness of sidewall portions of the first conductive liner.   
     
     
         2 . The memory device of  claim 1 , wherein the first conductive liner and the second conductive liner have different material compositions. 
     
     
         3 . The memory of  claim 1 , wherein the thickness of the sidewall portion of the first conductive liner is greater than the thickness of the sidewall portion of the second conductive liner. 
     
     
         4 . The memory of  claim 1 , wherein the thickness of the sidewall portion of the first conductive liner is less than the thickness of the sidewall portion of the second conductive liner. 
     
     
         5 . The memory device of  claim 1 , wherein the metal oxide layer is characterized by having a programmable resistance. 
     
     
         6 . The memory of  claim 1 , wherein the electrode surface of the interlayer conductor includes a top surface of the second conductive plug, the top surface consisting essentially of a metal, and the metal oxide layer comprises an oxide of said metal. 
     
     
         7 . The memory device of  claim 1 , wherein the first conductive plug and the second conductive plug have different material compositions. 
     
     
         8 . The memory device of  claim 1 , wherein the first conductive liner and the first conductive plug have different material compositions. 
     
     
         9 . The memory device of  claim 1 , wherein the second conductive liner covers the first conductive plug and the first conductive liner. 
     
     
         10 . A method of making a memory cell, comprising:
 forming a via through an insulation layer;   forming a lower portion of an interlayer conductive element comprising:
 forming a first conductive liner contacting sidewalls of the via, and 
 forming a first conductive plug in the first conductive liner; 
   forming an upper portion of the conductive element comprising:
 forming a second conductive liner contacting a top surface of the first conductive plug and sidewalls of the via, and 
 forming a second conductive plug located within the second conductive liner; 
   forming a metal oxide layer on an end of the upper portion opposite an end adjacent to the lower portion; and   forming a top electrode layer contacting the metal oxide layer;   wherein the second conductive liner includes sidewall portions having a thickness different than a thickness of sidewall portions of the first conductive liner.   
     
     
         11 . The method of  claim 10 , wherein the first conductive liner and the second conductive liner are formed of material with different material compositions. 
     
     
         12 . The method of  claim 10 , wherein the thickness of the sidewall portion of the first conductive liner is greater than the thickness of the sidewall portion of the second conductive liner. 
     
     
         13 . The method of  claim 10 , wherein the thickness of the sidewall portion of the first conductive liner is less than the thickness of the sidewall portion of the second conductive liner. 
     
     
         14 . The method of  claim 10 , wherein the metal oxide layer is characterized by having a programmable resistance. 
     
     
         15 . The method of  claim 10 , wherein forming the metal oxide layer includes oxidizing a portion of the second conductive plug. 
     
     
         16 . The method of  claim 10 , wherein the first conductive plug and the second conductive plug have different material compositions. 
     
     
         17 . The method of  claim 10 , wherein the first conductive plug and the second conductive plug have the same material composition. 
     
     
         18 . The method of  claim 10 , wherein the first conductive liner and the first conductive plug have different material compositions. 
     
     
         19 . The method of  claim 10 , wherein the second conductive liner covers the first conductive plug and the first conductive liner. 
     
     
         20 . An integrated circuit comprising:
 an array of memory cells, the memory cells comprising;
 a top electrode; 
 a metal oxide layer contacting the top electrode; and 
 an interlayer conductor having an electrode surface contacting the metal oxide layer; 
 wherein the interlayer conductor comprises an upper portion including the electrode surface and a lower portion; 
 wherein the lower portion comprising a first conductive liner and a first conductive plug in the first conductive liner and the upper portion comprising a second conductive liner and a second conductive plug in the second conductive liner; and 
 wherein the second conductive liner includes sidewall portions having a thickness different than a thickness of sidewall portions of the first conductive liner; and 
   control circuitry to control application of bias arrangement supply voltages.