Gate Formation Memory by Planarization

Abstract

Semiconductor devices and methods of producing the devices are disclosed. The devices are formed by forming a gate structure on a substrate. The gate structure includes a charge trapping dielectric formed between the substrate and a first poly layer. A top dielectric is formed over the poly layer and a sidewall dielectric is formed on a side of the poly layer. A second poly layer is formed over the gate structure such that a portion of the second poly layer includes a vertical portion that is in contact with the sidewall dielectric and a top portion that is in contact with the top dielectric. The top portion of the second poly layer can then be removed through, for instance, planarization.

1 - 17 . (canceled) 
     
     
         18 . A semiconductor device, comprising:
 a substrate;   a gate structure formed on the substrate, wherein the gate structure comprises
 a charge trapping dielectric formed between the substrate and a first poly layer, and 
 a sidewall dielectric formed on a first side of the first poly layer; and 
   a second poly layer adjacent to the gate structure wherein the second poly layer includes a portion that is in contact with the sidewall dielectric.   
     
     
         19 . The device of claim  1 , wherein a height of the gate structure is substantially the same as a height of the second poly layer. 
     
     
         20 . The device of claim  1 , wherein the device is configured as a split-gate memory cell. 
     
     
         21 . The device of claim  3 , wherein the gate structure is configured as a memory gate. 
     
     
         22 . The device of claim  3 , wherein the second poly layer and the sidewall dielectric are configured as a select gate. 
     
     
         23 . The device of claim  1 , wherein the charge trapping dielectric comprises an oxide layer and a nitride layer. 
     
     
         24 . The device of claim  1 , wherein the first sidewall dielectric comprises an oxide layer. 
     
     
         25 . A integrated circuit (IC) device, comprising:
 a substrate and a plurality of devices formed on the substrate, the plurality of devices comprising at least:
 a first device formed on the substrate, the first device comprising:
 a first gate structure, the first gate structure comprising a first charge trapping dielectric formed between the substrate and a first poly layer, and a first sidewall dielectric formed on a first side of the first poly layer; and 
 a second poly layer adjacent to the first gate structure wherein the second poly layer is in contact with the first sidewall dielectric; and 
 
 a second device formed on the substrate, the second device comprising:
 a second gate structure, the second gate structure comprising a second charge trapping dielectric formed between the substrate and a third poly layer, and a second sidewall dielectric formed on a second side of the third poly layer; and 
 a fourth poly layer adjacent to the second gate structure wherein the fourth poly layer is in contact with the second sidewall dielectric. 
 
   
     
     
         26 . The IC device of claim  8 , wherein the first device further comprises a third side of the first poly layer which is on the opposite side of the first poly layer from the first sidewall dielectric, and the second device further comprises a fourth side of the third poly layer which is on the opposite side of the third poly layer from the second sidewall dielectric, and wherein the first device and the second device are disposed on the substrate such that the third side of the first poly layer and the fourth side of the third poly layer are adjacent but not in direct contact. 
     
     
         27 . The IC device of claim  9 , wherein the substrate disposed between the third side of the first poly layer and the fourth side of the third poly layer is configured to act as a source to the first device and the second device. 
     
     
         28 . The IC device of claim  10 , wherein the first device and the second device are configured as split-gate memory cells. 
     
     
         29 . The IC device of claim  11 , wherein the first gate structure is configured as a first memory gate and the second gate structure is configured as a second memory gate. 
     
     
         30 . The IC device of claim  11 , wherein the second poly layer and the first sidewall dielectric are configured as a first select gate, and wherein the fourth poly layer and the second sidewall dielectric are configured as a second select gate. 
     
     
         31 . The IC device of claim  9 , wherein the first device further comprises a third sidewall dielectric formed on the third side of the first poly layer and wherein the second device further comprises a fourth sidewall dielectric formed on the fourth side of the third poly layer. 
     
     
         32 . The IC device of claim  8 , wherein a height of the second poly layer and a height of the fourth poly layer are substantially the same. 
     
     
         33 . The IC device of claim  16 , wherein a height of the first gate structure, the height of the second poly layer, a height of the second gate structure, and the height of the fourth poly layer are substantially the same. 
     
     
         34 . A method of forming an integrated circuit (IC) device, comprising:
 forming, on a substrate, a first gate structure comprising a first charge trapping dielectric formed between the substrate and a first poly layer, and a first sidewall dielectric on a first side of the first poly layer;   forming, on the substrate, adjacent to but not in direct contact with the first gate structure, a second gate structure comprising a second charge trapping dielectric formed between the substrate and a second poly layer, and a second sidewall dielectric on a second side of the second poly layer;   forming a third poly layer over the first gate structure and over the second gate structure such that the third poly layer includes a first vertical portion that is in contact with the first sidewall dielectric, a second vertical portion that is in contact with the second sidewall dielectric, and a top portion; and   removing the top portion.   
     
     
         35 . The method of claim  17 , further comprising forming a first memory gate from the first gate structure and a second memory gate from the second gate structure, and forming a first select gate from the first vertical portion and a second select gate from the second vertical portion. 
     
     
         36 . The method of  claim 18 , further comprising forming the first gate structure and the second gate structure such that a third side of the first poly layer which is on the opposite side of the first poly layer from the first sidewall dielectric and a fourth side of the third poly layer which is on the opposite side of the third poly layer from the second sidewall dielectric are adjacent but not in direct contact. 
     
     
         37 . The method of  claim 19 , further comprising configuring the substrate between the first device and the second device to be a source to the first memory gate and the second memory gate.