Non-volatile Split Gate Memory Device And A Method Of Operating Same

Abstract

A non-volatile memory device that a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is in the semiconductor substrate arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. A negative charge pump circuit generates a first negative voltage. A control circuit receives a command signal and generates a plurality of control signals, in response thereto and applies the first negative voltage to the word line of the unselected memory cells. During the operations of program, read or erase, a negative voltage can be applied to the word lines of the unselected memory cells.

What is claimed is: 
     
         1 . A non-volatile memory device comprising:
 a semiconductor substrate of a first conductivity type;   an array of non-volatile memory cells in the semiconductor substrate arranged in a plurality of rows and columns, each memory cell comprising:   a first region on a surface of the semiconductor substrate of a second conductivity type;   a second region on the surface of the semiconductor substrate of the second conductivity type;   a channel region between the first region and the second region;   a word line overlying a first portion of the channel region and insulated therefrom, and adjacent to the first region and having little or no overlap with the first region;   a floating gate overlying a second portion of the channel region, adjacent to the first portion, and insulated therefrom and adjacent to the second region;   a coupling gate overlying the floating gate;   a bit line connected to the first region;   a negative charge pump circuit for generating a first negative voltage; and   a control circuit for receiving a command signal and for generating a plurality of control signals to control the application of the first negative voltage to the coupling gate of the selected memory cells, in response thereto, wherein said control circuit comprises a current limiter in the high voltage decoder for supplying positive or negative high voltages to said memory cells.   
     
     
         2 . A non-volatile memory device comprising:
 a semiconductor substrate of a first conductivity type;   an array of non-volatile memory cells in the semiconductor substrate arranged in a plurality of rows and columns, each memory cell comprising:   a first region on a surface of the semiconductor substrate of a second conductivity type;   a second region on the surface of the semiconductor substrate of the second conductivity type;   a channel region between the first region and the second region;   a word line overlying a first portion of the channel region and insulated therefrom, and adjacent to the first region and having little or no overlap with the first region;   a floating gate overlying a second portion of the channel region, adjacent to the first portion, and insulated therefrom and adjacent to the second region;   a coupling gate overlying the floating gate;   a bit line connected to the first region;   a negative charge pump circuit for generating a first negative voltage; and   a control circuit for receiving a command signal and for generating a plurality of control signals to control the application of the first negative voltage to the coupling gate of the selected memory cells, in response thereto, wherein said control circuit comprises a current limiter in a high voltage decoder for supplying an erase voltage on the word line to said memory cells.   
     
     
         3 . A non-volatile memory device comprising:
 a semiconductor substrate of a first conductivity type;   an array of non-volatile memory cells in the semiconductor substrate arranged in a plurality of rows and columns, each memory cell comprising:   a first region on a surface of the semiconductor substrate of a second conductivity type;   a second region on the surface of the semiconductor substrate of the second conductivity type;   a channel region between the first region and the second region;   a word line overlying a first portion of the channel region and insulated therefrom, and adjacent to the first region and having little or no overlap with the first region;   a floating gate overlying a second portion of the channel region, adjacent to the first portion, and insulated therefrom and adjacent to the second region;   a coupling gate overlying the floating gate;   a bit line connected to the first region;   a negative charge pump circuit for generating a first negative voltage; and   a control circuit for receiving a command signal and for generating a plurality of control signals to control the application of the first negative voltage to the coupling gate of the selected memory cells, in response thereto, wherein said control circuit comprises a current limiter in a high voltage decoder for supplying a voltage on the coupling gate of said memory cells.   
     
     
         4 . The non-volatile memory device of  claim 3  wherein said control circuit comprises a current limiter in a high voltage decoder for supplying a voltage on the coupling gate of said memory cells during program or erase operations. 
     
     
         5 . A non-volatile memory device comprising:
 a semiconductor substrate of a first conductivity type;   an array of non-volatile memory cells in the semiconductor substrate arranged in a plurality of rows and columns, each memory cell comprising:   a first region on a surface of the semiconductor substrate of a second conductivity type;   a second region on the surface of the semiconductor substrate of the second conductivity type;   a channel region between the first region and the second region;   a word line overlying a first portion of the channel region and insulated therefrom, and adjacent to the first region and having little or no overlap with the first region;   a floating gate overlying a second portion of the channel region, adjacent to the first portion, and insulated therefrom and adjacent to the second region;   a coupling gate overlying the floating gate;   a bit line connected to the first region;   a negative charge pump circuit for generating a first negative voltage; and   a control circuit for receiving a command signal and for generating a plurality of control signals to control the application of the first negative voltage to the coupling gate of the selected memory cells, in response thereto, wherein said control circuit comprises a high voltage latch in a high voltage decoder for supplying voltages to said memory cells in program or erase or read operations.   
     
     
         6 . A non-volatile memory device comprising:
 a semiconductor substrate of a first conductivity type;   an array of non-volatile memory cells in the semiconductor substrate arranged in a plurality of rows and columns, each memory cell comprising:   a first region on a surface of the semiconductor substrate of a second conductivity type;   a second region on the surface of the semiconductor substrate of the second conductivity type;   a channel region between the first region and the second region;   a word line overlying a first portion of the channel region and insulated therefrom, and adjacent to the first region and having little or no overlap with the first region;   a floating gate overlying a second portion of the channel region, adjacent to the first portion, and insulated therefrom and adjacent to the second region;   a coupling gate overlying the floating gate;   a bit line connected to the first region;   a negative charge pump circuit for generating a first negative voltage; and   a control circuit for receiving a command signal and for generating a plurality of control signals to control the application of the first negative voltage to the coupling gate of the selected memory cells, in response thereto, wherein said control circuit comprises a high voltage level shifter in a high voltage decoder for supplying voltages to said memory cells in program or erase or read operations.   
     
     
         7 . A non-volatile memory device comprising:
 a semiconductor substrate of a first conductivity type;   an array of non-volatile memory cells in the semiconductor substrate arranged in a plurality of rows and columns, each memory cell comprising:   a first region on a surface of the semiconductor substrate of a second conductivity type;   a second region on the surface of the semiconductor substrate of the second conductivity type;   a channel region between the first region and the second region;   a word line overlying a first portion of the channel region and insulated therefrom, and adjacent to the first region and having little or no overlap with the first region;   a floating gate overlying a second portion of the channel region, adjacent to the first portion, and insulated therefrom and adjacent to the second region;   a coupling gate overlying the floating gate;   a bit line connected to the first region;   a negative charge pump circuit for generating a first negative voltage; and   a control circuit for receiving a command signal and for generating a plurality of control signals to control the application of the first negative voltage to the coupling gate of the selected memory cells, in response thereto, wherein said control circuit comprises a low voltage latch in a high voltage decoder for supplying voltages to said memory cells in program or erase or read operations.   
     
     
         8 . A non-volatile memory device comprising:
 a semiconductor substrate of a first conductivity type;   an array of non-volatile memory cells in the semiconductor substrate arranged in a plurality of rows and columns, each memory cell comprising:   a first region on a surface of the semiconductor substrate of a second conductivity type;   a second region on the surface of the semiconductor substrate of the second conductivity type;   a channel region between the first region and the second region;   a word line overlying a first portion of the channel region and insulated therefrom, and adjacent to the first region and having little or no overlap with the first region;   a floating gate overlying a second portion of the channel region, adjacent to the first portion, and insulated therefrom and adjacent to the second region;   a coupling gate overlying the floating gate;   a bit line connected to the first region;   a negative charge pump circuit for generating a first negative voltage;   a control circuit for receiving a command signal and for generating a plurality of control signals to control the application of the first negative voltage to the coupling gate of the selected memory cells, in response thereto; and   a low voltage decoder for supplying voltages to said memory cells in program or erase or read operations.   
     
     
         9 . The non-volatile memory device of  claim 8 , wherein the low voltage decoder comprises an isolation transistor in a wordline driver for supplying voltages to said memory cells in program, erase, or read operations.