High-Performance Instruction Cache System and Method

Abstract

A high performance instruction cache method for facilitating operation of a processor core coupled to a first memory containing executable instructions, and a second memory with a faster speed than the first memory is provided. The method includes examining instructions from the first memory filled into the second memory and extracting instruction information containing at least branch information. The method also includes creating a plurality of tracks based on the extracted instruction information. Further, the method includes filling at least one or more instructions that are possibly executed by the processor core from the first memory into the second memory based on one or more tracks from a plurality of instruction tracks.

1 .- 20 . (canceled) 
     
     
         21 . A high performance instruction cache method for facilitating operation of a processor core coupled to a second memory containing executable instructions, and a first memory with a faster speed than the second memory, the method comprising:
 examining instructions filled from the second memory to the first memory;   extracting instruction information containing at least branch information;   based on the extracted instruction information, creating a plurality of tracks in a track table, wherein a track in the track table corresponds one-to-one to an instruction block in the first memory; and   based on one or more tracks from a plurality of instruction tracks, filling at least one or more instructions that are possibly executed by the processor core from the first memory into the second memory;   wherein: the second memory is a set associative memory, and the first memory is a fully associative memory.