Display apparatus

Abstract

A display apparatus includes a gate line, a data line, and a pixel. The pixel includes first and second pixels displaying grayscales different from each other in response to a data voltage provided through the data line. The first pixel includes a first transistor including a gate electrode connected to the gate line and a first terminal connected to the data line and a first liquid crystal capacitor connected to a second terminal of the first transistor. The second pixel includes a second transistor including a gate electrode connected to the gate line and a first terminal connected to the second terminal of the first transistor and a second liquid crystal capacitor connected to a second terminal of the second transistor.

What is claimed is: 
     
         1 . A display apparatus comprising:
 a gate line;   a data line; and   a pixel connected to the gate line and the data line, the pixel comprising a first pixel and a second pixel, which display grayscales different from each other in response to a data voltage provided through the data line,   the first pixel comprising:
 a first transistor comprising a gate electrode connected to the gate line and a first terminal connected to the data line; and 
 a first liquid crystal capacitor connected to a second terminal of the first transistor, and 
   the second pixel comprising:
 a second transistor comprising a gate electrode connected to the gate line and a first terminal connected to the second terminal of the first transistor; and 
 a second liquid crystal capacitor connected to a second terminal of the second transistor. 
   
     
     
         2 . The display apparatus of  claim 1 , wherein the second terminal of the first transistor has a first level after a predetermined time lapses from a rising time of a gate signal applied to the gate line, and the second terminal of the second transistor has a second level lower than the first level after a predetermined time lapses from the rising time of the gate signal applied to the gate line. 
     
     
         3 . The display apparatus of  claim 1 , wherein a voltage level of the second terminal of the second transistor increases slower than a voltage level of the second terminal of the first transistor. 
     
     
         4 . The display apparatus of  claim 1 , wherein the first and second transistors have different resistances from each other while being turned on. 
     
     
         5 . The display apparatus of  claim 1 , wherein a first electrode of the first liquid crystal capacitor is connected to the second terminal of the first transistor, a second other electrode of the first liquid crystal capacitor is applied with a common voltage, a first electrode of the second liquid crystal capacitor is connected to the second terminal of the second transistor, and a second other electrode of the second liquid crystal capacitor is applied with a common voltage. 
     
     
         6 . The display apparatus of  claim 1 , wherein the first pixel further comprises a first storage capacitor having a first electrode connected to the second terminal of the first transistor and a second electrode applied with a storage voltage, and the second pixel further comprises a second storage capacitor having a first electrode connected to the second terminal of the second transistor and a second other electrode applied with the storage voltage. 
     
     
         7 . The display apparatus of  claim 1 , wherein the second pixel further comprises an auxiliary resistor connected to the second transistor in series. 
     
     
         8 . The display apparatus of  claim 7 , wherein the auxiliary resistor is connected between the second terminal of the first transistor and the first terminal of the second transistor. 
     
     
         9 . The display apparatus of  claim 7 , wherein the auxiliary resistor comprises at least one of amorphous silicon and intrinsic silicon. 
     
     
         10 . A display apparatus comprising:
 a first gate line;   a second gate line disposed adjacent to the first gate line;   a data line; and   a pixel connected to the first gate line, the second gate line, and the data line, the pixel comprising a first pixel and a second pixel, which display two grayscales different from each other on the basis of a data voltage provided through the data line,   the first pixel comprising:
 a first transistor comprising a gate electrode connected to the first gate line and a first terminal connected to the data line; and 
 a first liquid crystal capacitor connected to a second terminal of the first transistor, and 
   the second pixel comprising:
 a second transistor comprising a gate electrode connected to the second gate line and a first terminal connected to a second terminal of the first transistor; and 
 a second liquid crystal capacitor connected to a second terminal of the second transistor. 
   
     
     
         11 . The display apparatus of  claim 10 , wherein a first gate signal applied to the first gate line and a second gate signal applied to the second gate line are in a high state during a same horizontal scan period. 
     
     
         12 . The display apparatus of  claim 11 , wherein the first gate signal has a first pulse height and the second gate signal has a second pulse height lower than the first pulse height. 
     
     
         13 . The display apparatus of  claim 11 , wherein the second terminal of the first transistor has a first level after a predetermined time lapses from a rising time of the first gate signal, and the second terminal of the second transistor has a second level lower than the first level after a predetermined time lapses from the rising time of the first gate signal. 
     
     
         14 . The display apparatus of  claim 10 , wherein the second pixel further comprises a third transistor connected to the second transistor in series. 
     
     
         15 . The display apparatus of  claim 14 , wherein the third transistor comprises a gate electrode connected to the first gate line, a first terminal connected to the second terminal of the second transistor, and a second terminal of the third transistor is connected to the second liquid crystal capacitor. 
     
     
         16 . The display apparatus of  claim 15 , wherein the second terminal of the first transistor has a first level after a predetermined time lapses from a rising time of a gate signal applied to the first gate line, and the second terminal of the second transistor has a second level lower than the first level after a predetermined time lapses from the rising time of the gate signal applied to the gate line. 
     
     
         17 . A display apparatus comprising:
 a gate line;   a data line; and   a pixel connected to the gate line and the data line, the pixel comprising a first pixel comprising a first transistor and a second pixel comprising a second transistor,   wherein the first pixel and the second pixel display grayscales different from each other in response to a data voltage provided through the data line, and   wherein a first non-gate electrode of the first transistor is connected to a first non-gate electrode of the second transistor.   
     
     
         18 . The display apparatus of  claim 17 , wherein gate electrodes of each transistor are connected to the gate line and a second other non-gate electrode of the first transistor is connected to the data line. 
     
     
         19 . The display apparatus of  claim 18 , wherein the first non-gate electrode of the first transistor is connected to a first liquid crystal capacitor, and a second other non-gate electrode of the second transistor is connected to a second other liquid crystal capacitor. 
     
     
         20 . The display apparatus of  claim 19 , wherein during a period after application of a gate on voltage to the gate line, a voltage of the first non-gate electrode of the first transistor increases more quickly than a voltage of the second non-gate electrode of the second transistor.