Methods for preventing oxidation damage during finfet fabrication

Abstract

Embodiments of the present invention provide improved methods for fabricating field effect transistors such as finFETs. Stressor regions are used to increase carrier mobility. However, subsequent processes such as deposition of flowable oxide and annealing can damage the stressor regions, diminishing the amount of stress that is induced. Embodiments of the present invention provide a protective layer of silicon or silicon oxide over the stressor regions prior to the flowable oxide deposition and anneal.

1 .- 20 . (canceled) 
     
     
         21 . A semiconductor structure, comprising:
 a gate;   a plurality of stressor regions adjacent to the gate;   a contact etch stopping layer disposed on at least a part of each at least one side portion of the gate and at least one side portion of each of the plurality of stressor regions; and   a silicon oxide layer disposed on the gate and plurality of stressor regions.   
     
     
         22 . The semiconductor substrate of  claim 21 , wherein the contact etch stopping layer comprises silicon nitride. 
     
     
         23 . The semiconductor substrate of  claim 21 , wherein the silicon oxide layer has a thickness ranging from about 50 angstroms to about 150 angstroms. 
     
     
         24 . The semiconductor substrate of  claim 21 , wherein the plurality of stressor regions comprise a silicon germanium region. 
     
     
         25 . The semiconductor substrate of  claim 21 , wherein the plurality of stressor regions comprise a silicon phosphorous region. 
     
     
         26 . The semiconductor substrate of  claim 21 , further comprising a spacer layer disposed on at least a part of each at least one side portion of the gate. 
     
     
         27 . The semiconductor substrate of  claim 26 , wherein the spacer layer comprises silicon nitride. 
     
     
         28 . The semiconductor substrate of  claim 21 , further comprising a pad nitride layer disposed over the gate. 
     
     
         29 . A semiconductor structure, comprising:
 a gate;   a plurality of stressor regions adjacent to the gate;   a silicon oxide layer disposed on the gate and plurality of stressor regions; and   a flowable oxide disposed on the plurality of stressor regions   
     
     
         30 . The semiconductor substrate of  claim 29 , wherein the silicon oxide layer has a thickness ranging from about 10 angstroms to about 50 angstroms. 
     
     
         31 . The semiconductor substrate of  claim 29 , wherein the plurality of stressor regions comprise a silicon germanium region. 
     
     
         32 . The semiconductor substrate of  claim 29 , wherein the plurality of stressor regions comprise a silicon phosphorous region. 
     
     
         33 . The semiconductor substrate of  claim 29 , further comprising a spacer layer disposed on at least a part of each at least one side portion of the gate. 
     
     
         34 . The semiconductor substrate of  claim 33 , wherein the spacer layer comprises silicon nitride. 
     
     
         35 . The semiconductor substrate of  claim 29 , further comprising a pad nitride layer disposed over the gate.