Trench Gated Power Device With Multiple Trench Width and its Fabrication Process

Abstract

Power devices, and related process, where both gate and field plate trenches have multiple stepped widths, using self-aligned process steps.

1 - 32 . (canceled) 
     
     
         33 . A method of fabricating a power semiconductor device, comprising:
 etching a plurality of trenches into a semiconductor mass, using at least two sidewall spacer operation to form individual ones of said trenches with a stepped width;   providing a dielectric which fills lowermost portions of first ones of said trenches, but not second ones of said trenches;   forming insulated gate electrodes in said first trenches, but not in said second trenches;   forming a first-conductivity-type source region and a second-conductivity-type body region in proximity to said first trenches;   forming second-conductivity-type body contact regions in said sc mass adjacent said second trenches; and   electrically connecting said source, gate, and body contact regions to provide an operative active device.   
     
     
         34 . The method of  claim 33 , wherein said first conductivity type is n-type, and said second conductivity type is p-type. 
     
     
         35 . The method of  claim 33 , wherein said semiconductor mass consists essentially of silicon. 
     
     
         36 . The method of  claim 33 , wherein said gate electrodes are made of doped polysilicon. 
     
     
         37 . The method of  claim 33 , wherein said middle portion of each said trench has a greater vertical extent than said bottom portion thereof, and said bottom portion of each said trench has a greater vertical extent than said top portion thereof. 
     
     
         38 . The method of  claim 33 , wherein said gate electrode does not extend into said bottom portion of said first trench, and said field plate electrode does extend into said bottom portion of said second trench. 
     
     
         39 . The method of  claim 33 , wherein doping for said body region is provided by a well diffusion process. 
     
     
         40 . The method of  claim 33 , further comprising the intermediate step of implanting second-conductivity-type dopants into said second trenches, at a time when said first trenches are covered or filled and second trenches are not, to thereby form localized regions of reduced net first-conductivity-type doping below said second trenches. 
     
     
         41 . A method of fabricating a power semiconductor device, comprising:
 etching a plurality of trenches into a semiconductor mass, using at least two sidewall spacer operation to form individual ones of said trenches with a stepped width;   providing a dielectric which fills lowermost portions of first ones of said trenches, but not second ones of said trenches;   forming insulated gate electrodes in said first trenches, but not in said second trenches;   forming a first-conductivity-type source region and a second-conductivity-type body region in proximity to said first trenches;   forming second-conductivity-type body contact regions in said sc mass adjacent said second trenches; and   electrically connecting said source, gate, and body contact regions to provide an operative active device;   wherein said semiconductor mass is initially an epitaxial structure including a first-conductivity-type epitaxial layer on a first-conductivity-type substrate, and said substrate is much more heavily doped than said epitaxial layer.   
     
     
         42 . The method of  claim 33 , wherein said semiconductor mass is initially an epitaxial structure including a first-conductivity-type epitaxial layer on a first-conductivity-type substrate, and said substrate is much more heavily doped than said epitaxial layer; and further comprising the additional step of introducing additional first-conductivity-type dopants into upper portions, but not into lower portions, of said epitaxial layer, at depths deeper than the depth of said body region. 
     
     
         43 . A method of fabricating a power semiconductor device, comprising:
 etching a plurality of trenches into a semiconductor mass, using at least two sidewall spacer operation to form individual ones of said trenches with a stepped width;   providing a dielectric which fills lowermost portions of first ones of said trenches, but not second ones of said trenches;   forming insulated gate electrodes in said first trenches, but not in said second trenches;   forming a first-conductivity-type source region and a second-conductivity-type body region in proximity to said first trenches;   forming second-conductivity-type body contact regions in said sc mass adjacent said second trenches; and   electrically connecting said source, gate, and body contact regions to provide an operative active device;   further comprising the additional step, before forming insulated gate electrodes in said first trenches, of forming insulated shield electrodes in said first trenches.