Nonvolatile memory devices having single-layered gates and methods of fabricating the same

Abstract

A nonvolatile memory device includes an active region extending in a first direction and including a source region and a drain region that are respectively disposed at both ends of the active region, a gate electrode pattern extending in a second direction and disposed between the source region and the drain region, wherein the second direction extends across the first direction, a gate insulation pattern disposed between the gate electrode pattern and the active region, a source contact plug and a drain contact plug respectively coupled to the source region and the drain region, and a coupling contact plug disposed over the gate electrode pattern and insulated from the gate electrode pattern.

What is claimed is: 
     
         1 . A nonvolatile memory device comprising:
 an active region extending in a first direction and including a source region and a drain region that are respectively disposed at both ends of the active region;   a gate electrode pattern extending in a second direction and disposed between the source region and the drain region, wherein the second direction extends across the first direction;   a gate insulation pattern disposed between the gate electrode pattern and the active region;   a source contact plug and a drain contact plug respectively coupled to the source region and the drain region; and   a coupling contact plug disposed over the gate electrode pattern and insulated from the gate electrode pattern.   
     
     
         2 . The nonvolatile memory device of  claim 1 , wherein the gate electrode pattern is formed of a single polysilicon layer. 
     
     
         3 . The nonvolatile memory device of  claim 1 , wherein the source contact plug, the drain contact plug, and the coupling contact plug include the same conductive material. 
     
     
         4 . The nonvolatile memory device of  claim 3 , wherein the same conductive material includes a tungsten material. 
     
     
         5 . The nonvolatile memory device of  claim 1 , wherein the coupling contact plug extends across the active region and overlaps with the gate electrode pattern. 
     
     
         6 . The nonvolatile memory device of  claim 5 ,
 wherein a width of the coupling contact plug measured along the first direction is substantially equal to a width of the gate electrode pattern measured along the first direction; and   wherein a length of the coupling contact plug measured along the second direction is greater than a length of the gate electrode pattern measured along the second direction.   
     
     
         7 . The nonvolatile memory device of  claim 6 , wherein an entire portion of the gate electrode pattern overlaps with a portion of the coupling contact plug. 
     
     
         8 . The nonvolatile memory device of  claim 1 , further comprising:
 a first silicide layer disposed between the source region and the source contact plug;   a second silicide layer disposed between the drain region and the drain contact plug; and   an insulation layer disposed between the gate electrode pattern and the coupling contact plug,   wherein the insulation layer is a silicide blocking layer having a multi-layered structure.   
     
     
         9 . The nonvolatile memory device of  claim 8 , wherein the silicide blocking layer includes a first insulation layer, a second insulation layer, and a third insulation layer which are sequentially stacked. 
     
     
         10 . The nonvolatile memory device of  claim 9 , wherein the second insulation layer has an etch selectivity different from the third insulation layer. 
     
     
         11 . The nonvolatile memory device of  claim 10 , wherein the second insulation layer includes a nitride layer and the third insulation layer includes an oxide layer. 
     
     
         12 . A nonvolatile memory device comprising:
 a source region and a drain region disposed in a substrate and spaced apart from each other;   a first silicide layer and a second silicide layer respectively disposed over the source region and the drain region;   a gate insulation pattern disposed over a channel region and between the source region and the drain region;   a gate electrode pattern disposed over the gate insulation pattern;   an insulation spacer disposed over sidewalls of the gate electrode pattern and the gate insulation pattern;   a silicide blocking layer covering the insulation spacer and the gate electrode pattern and having a multi-layered structure;   an etch buffer layer disposed over the silicide blocking layer and the first and second silicide layers;   an interlayer insulation layer disposed over the etch buffer layer;   a source contact plug and a drain contact plug penetrating the interlayer insulation layer to respectively contact the first silicide layer and the second silicide layer; and   a coupling contact plug penetrating the interlayer insulation layer and the etch buffer layer and extending to the silicide blocking layer.   
     
     
         13 . The nonvolatile memory device of  claim 12 , wherein the gate electrode pattern is formed of a single polysilicon layer. 
     
     
         14 . The nonvolatile memory device of  claim 12 , wherein the silicide blocking layer includes a first insulation layer, a second insulation layer, and a third insulation layer which are sequentially stacked. 
     
     
         15 . The nonvolatile memory device of  claim 14 , wherein the second insulation layer has an etch selectivity different from the third insulation layer. 
     
     
         16 . The nonvolatile memory device of  claim 15 , wherein the second insulation layer includes a nitride layer and the third insulation layer includes an oxide layer. 
     
     
         17 . The nonvolatile memory device of  claim 12 , wherein an etch rate of the etch buffer layer is lower than an etch rate of the interlayer insulation layer. 
     
     
         18 . The nonvolatile memory device of  claim 17 , wherein the etch buffer layer serve as an etch stop layer when the interlayer Insulation layer is etched. 
     
     
         19 . The nonvolatile memory device of  claim 18 , wherein the interlayer insulation layer includes an oxide layer and the etch buffer layer includes a nitride layer. 
     
     
         20 . The nonvolatile memory device of  claim 12 , wherein the source contact plug, the drain contact plug, and the coupling contact plug include the same conductive material. 
     
     
         21 . A method of fabricating a nonvolatile memory device, the method comprising:
 forming a gate Insulation pattern and a gate electrode pattern over a substrate;   forming an insulation spacer over sidewalls of the gate insulation pattern and the gate electrode pattern;   forming a source region and a drain region in the substrate which are adjacent to both sidewalls of the gate electrode pattern;   forming a silicide blocking layer having a multi-layered structure over the gate insulation pattern and the insulation spacer to expose the source region and the drain region;   forming a first silicide layer and a second silicide layer over the exposed source region and the exposed drain region, respectively;   forming an etch buffer layer over the first and second silicide layers and the silicide blocking layer;   forming an interlayer insulation layer over the etch buffer layer;   patterning the interlayer insulation layer to form a source contact hole exposing the first silicide layer, a drain contact hole exposing the second silicide layer, and a coupling contact hole exposing the silicide blocking layer; and   forming a source contact plug, a drain contact plug, and a coupling contact plug in the source contact hole, the drain contact hole, and the coupling contact hole, respectively,   wherein each of the source contact plug, the drain contact plug, and the coupling contact plug includes a metal layer.