US2016211321A1PendingUtilityA1

Buried Trench Isolation in Integrated Circuits

Assignee: CYPRESS SEMICONDUCTOR CORPPriority: Mar 12, 2014Filed: Feb 1, 2016Published: Jul 21, 2016
Est. expiryMar 12, 2034(~7.6 yrs left)· nominal 20-yr term from priority
H10P 95/906H10W 10/021H10W 10/20H10W 10/17H10W 10/014H10D 62/832H10D 62/124H10D 62/115H01L 29/0684H01L 29/161H01L 29/0649
51
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Claims

Abstract

A system for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) is disclosed herein. An integrated circuit (IC) comprises a substrate, a first device, a second device, and an isolator. The isolator is positioned between first and second device. The isolator comprises one or more cavities. The isolator may be filled with dielectric material.

Claims

exact text as granted — not AI-modified
1 - 4 . (canceled) 
     
     
         5 . An integrated circuit (IC) comprising:
 a substrate;   a first device and a second device formed on a surface of the substrate, the first device and the second device each comprising a gate structure; and   an isolator arranged to isolate the first device and the second device from one another, wherein the isolator comprises at least one cavity buried in the substrate, and wherein the isolator is positioned between the first and second devices.   
     
     
         6 . The IC of  claim 5 , wherein the at least one cavity is filled with a dielectric material. 
     
     
         7 . The IC of  claim 6 , wherein the dielectric material is air. 
     
     
         8 . The IC of  claim 6 , further comprising a seed material disposed between a top of the dielectric material and the surface of the substrate, wherein the seed material is configured to smooth a reshaping of the substrate over the isolator. 
     
     
         9 . The IC of  claim 8 , wherein the seed material comprises silicon or germanium. 
     
     
         10 . The IC of  claim 5 , wherein a vertical cross-section of the at least one cavity has a rectangular perimeter. 
     
     
         11 . The IC of  claim 5 , wherein a vertical cross-section of the at least one cavity has a height greater than a width. 
     
     
         12 . The IC of  claim 5 , wherein the isolator comprises at least two cavities buried in the substrate. 
     
     
         13 . The IC of  claim 12 , wherein the at least two cavities are aligned along a line that is substantially perpendicular to the surface of the substrate. 
     
     
         14 . An integrated circuit (IC) comprising:
 a substrate;   a plurality of devices formed on a surface of the substrate; and   an isolation region arranged to isolate at least a first device and a second device of the plurality of devices from one another, wherein the isolation region:
 comprises at least one cavity buried in the substrate, wherein the cavity is filled with dielectric material; and 
 is positioned between the at least first and second devices. 
   
     
     
         15 . The integrated circuit of  claim 14 , wherein the dielectric material comprises oxide or nitride. 
     
     
         16 . The integrated circuit of  claim 14 , wherein the dielectric material comprises air. 
     
     
         17 . The integrated circuit of  claim 14 , wherein the isolation region comprises at least two cavities. 
     
     
         18 . The integrated circuit of  claim 17 , wherein the at least two cavities are aligned along a line that intersects with the surface of the substrate. 
     
     
         19 . The integrated circuit of  claim 14 , further comprising a seed material disposed between a top of the dielectric material and the surface of the substrate, wherein the seed material is configured to smooth a reshaping of the substrate over the isolation region. 
     
     
         20 . The integrated circuit of  claim 19 , wherein the seed material comprises silicon or germanium. 
     
     
         21 . An apparatus comprising:
 a substrate: and   an isolator disposed to isolate a first device and a second device formed on a surface of the substrate, wherein the isolator comprises at least one cavity filled with dielectric and buried in the substrate, and wherein the isolator is positioned between the first device and the second devices.   
     
     
         22 . The apparatus of  claim 21 , wherein the first device and second device each comprise a gate structure. 
     
     
         23 . The apparatus of  claim 21 , further comprising a seed material disposed between the dielectric and the substrate, wherein the seed material is configured to smooth reshaping of the substrate over the isolator. 
     
     
         24 . The apparatus of  claim 23 , wherein the seed material comprises silicon or germanium.

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