Manufacturing and evaluation method of a semiconductor device
Abstract
Provided is a method of manufacturing a semiconductor device which includes a semiconductor chip, an insulating board mounted with the semiconductor chip and having a wiring pattern, and a leadframe connected to the wiring pattern, the semiconductor chip, the wiring pattern and the leadframe being partially sealed with a sealing resin, wherein: an epoxy resin composition formed by adding 0.3 to 0.7 mass % of epoxysilane as a silane coupling agent to an epoxy resin is used as the sealing resin; and a copper member made of copper or a copper alloy and having an oxide film formed in the surface with a film thickness in a color indicated by an L* value in the range of 48 to 51, an a* value in the range of 40 to 49 and a b* value in the range of 24 to 40 is used as the leadframe and the wiring pattern.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A method for evaluating strength, comprising:
providing a bonding surface between a surface of an oxide film and a cured product of a resin formed on the surface of the oxide film in a molded article formed by integrating the resin with a copper member by insert molding; forming the copper member from copper or a copper alloy; determining adhesive strength of the bonding surface based upon a film thickness of the oxide film evaluated by an L* value, an a* value, and a b* value of the surface of the oxide film, the L* value, the a* value, and the b* value being chromatic values of a predetermined color system; and verifying whether each of the L* value is in the range of 48 to 51, the a* value is in the range of 40 to 49, and the b* value is in the range of 24 to 40.
2 . The method for evaluating strength according to claim 1 , wherein an epoxy resin composition is used as the resin.
3 . A semiconductor device, comprising:
a semiconductor chip; an insulating board mounted with the semiconductor chip and having a wiring pattern; and a leadframe connected to the wiring pattern; wherein the semiconductor chip, the wiring pattern, and the leadframe are partially sealed with a sealing resin; wherein the sealing resin includes an epoxy resin composition formed by adding 0.3 to 0.7 mass % of epoxysilane as a silane coupling agent to an epoxy resin; wherein the leadframe and the wiring pattern include copper or a copper alloy; wherein an oxide film having a thickness of between 20 nm and 40 nm is formed in the surfaces of the leadframe and the wiring pattern; and wherein the leadframe and the wiring pattern are in contact with the sealing resin.
4 . The method for evaluating strength according to claim 1 , wherein the color system is JIS Z 8729 color system.
5 . A method for evaluating strength, comprising:
determining an L* value, an a* value, and a b* value of a surface of an oxide film, wherein the L* value, the a* value, and the b* value are chromatic values of a predetermined color system; and determining a projected adhesive strength of bonding of the oxide film to a resin and a copper member based upon a film thickness of the oxide film evaluated based upon the L* value, the a* value, and the b* value, the determining including verifying if each of the L* value is in the range of 48 to 51, the a* value is in the range of 40 to 49, and the b* value is in the range of 24 to 40.Join the waitlist — get patent alerts
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