Data processing device and data processing method

Abstract

The present technology relates to a data processing device and a data processing method so that an LDPC code with a good bit error rate is provided. An LDPC encoder encodes by an LDPC code whose code length is 16200 bits and code rate is 8/15. The LDPC code includes information bits and parity bits. A parity check matrix H includes an information matrix part corresponding to the information bits of the LDPC code and a parity matrix part corresponding to the parity bits. The information matrix part of the parity check matrix H is represented by a parity check matrix initial value table that indicates a position of an element 1 of the information matrix part for each 360 columns. The present technology is applicable to a case in which LDPC encoding and LDPC decoding are performed.

1 . A data processing device, comprising:
 an encoder, which encodes information bits into an LDPC (low density parity check) code whose code length is 16200 bits and code rate is 8/15 based on a parity check matrix of the LDPC code,   the LDPC code including information bits and parity bits,   the parity check matrix including an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits,   the information matrix part being represented by a parity check matrix initial value table, and   the parity check matrix initial value table being a table indicating a position of an element 1 of the information matrix part for each 360 columns as   
       5 519 825 1871 2098 2478 2659 2820 3200 3294 3650 3804 3949 4426 4460 4503 4568 4590 4949 5219 5662 5738 5905 5911 6160 6404 6637 6708 6737 6814 7263 7412 
       81 391 1272 1633 2062 2882 3443 3503 3535 3908 4033 4163 4490 4929 5262 5399 5576 5768 5910 6331 6430 6844 6867 7201 7274 7290 7343 7350 7378 7387 7440 7554 
       105 975 3421 3480 4120 4444 5957 5971 6119 6617 6761 6810 7067 7353 
       6 138 485 1444 1512 2615 2990 3109 5604 6435 6513 6632 6704 7507 
       20 858 1051 2539 3049 5162 5308 6158 6391 6604 6744 7071 7195 7238 
       1140 5838 6203 6748 
       6282 6466 6481 6638 
       2346 2592 5436 7487 
       2219 3897 5896 7528 
       2897 6028 7018 
       1285 1863 5324 
       3075 6005 6466 
       5 6020 7551 
       2121 3751 7507 
       4027 5488 7542 
       2 6012 7011 
       3823 5531 5687 
       1379 2262 5297 
       1882 7498 7551 
       3749 4806 7227 
       2 2074 6898 
       17 616 7482 
       9 6823 7480 
       5195 5880 7559. 
     
     
         2 . The data processing device according to  claim 1 , wherein
 if a row of the parity check matrix initial table is represented by i and a parity length of the LDPC code is represented by M, the 2+360×(i−1)-th column of the parity check matrix is obtained by the cyclic shift of the 1+360×(i−1)-th column of the parity check matrix indicating a position of an element 1 in the parity check matrix initial value table downward by q=M/360.   
     
     
         3 . The data processing device according to  claim 2 , wherein
 as for the 1+360×(i−1)-th column of the parity check matrix,   an i-th row of the parity check matrix initial value table represents the row number of the element 1 of the 1+360×(i−1)-th column of the parity check matrix, and   as for each column from the 2+360×(i−1)-th column to a 360×i-th column being the column other than the 1+360×(i−1)-th column of the parity check matrix,   if an i-th row j-th column value of the parity check matrix initial value table is represented as h i, j  and the row number of a j-th element 1 of a w-th column of the parity check matrix H is represented as H w-j ,   a row number of the element 1 of the w-th column being the column other than the 1+360×(i−1)-th column of the parity check matrix is represented by the equation H w-j =mod {h i,j +mod((w−1), 360)×M/360, M).   
     
     
         4 . The data processing device according to  claim 1 , further comprising:
 a parity interleaver for interleaving only parity bits of the LDPC code.   
     
     
         5 . The data processing device according to  claim 1 , wherein
 the parity check matrix has no cycle-4.   
     
     
         6 . The data processing device according to  claim 1 , wherein
 the parity check matrix of the LDPC code belongs to an ensemble in which the performance threshold being Eb/No at which a BER starts to decrease is a predetermined value or smaller is found by multi-edge type density evolution.   
     
     
         7 . A data processing method, comprising:
 a step of encoding, which encodes information bits into an LDPC (low density parity check) code whose code length is 16200 bits and code rate is 8/15 based on a parity check matrix of the LDPC code,   the LDPC code including information bits and parity bits,   the parity check matrix including an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits,   the information matrix part being represented by a parity check matrix initial value table, and   the parity check matrix initial value table being a table indicating a position of an element 1 of the information matrix part for each 360 columns as   
       5 519 825 1871 2098 2478 2659 2820 3200 3294 3650 3804 3949 4426 4460 4503 4568 4590 4949 5219 5662 5738 5905 5911 6160 6404 6637 6708 6737 6814 7263 7412 
       81 391 1272 1633 2062 2882 3443 3503 3535 3908 4033 4163 4490 4929 5262 5399 5576 5768 5910 6331 6430 6844 6867 7201 7274 7290 7343 7350 7378 7387 7440 7554 
       105 975 3421 3480 4120 4444 5957 5971 6119 6617 6761 6810 7067 7353 
       6 138 485 1444 1512 2615 2990 3109 5604 6435 6513 6632 6704 7507 
       20 858 1051 2539 3049 5162 5308 6158 6391 6604 6744 7071 7195 7238 
       1140 5838 6203 6748 
       6282 6466 6481 6638 
       2346 2592 5436 7487 
       2219 3897 5896 7528 
       2897 6028 7018 
       1285 1863 5324 
       3075 6005 6466 
       5 6020 7551 
       2121 3751 7507 
       4027 5488 7542 
       2 6012 7011 
       3823 5531 5687 
       1379 2262 5297 
       1882 7498 7551 
       3749 4806 7227 
       2 2074 6898 
       17 616 7482 
       9 6823 7480 
       5195 5880 7559. 
     
     
         8 . A data processing device, comprising:
 an decoder, which decodes an LDPC (low density parity check) code provided from data transmitted from a transmitting device, which includes an encoder, which encodes information bits into an LDPC (low density parity check) code whose code length is 16200 bits and code rate is 8/15 based on a parity check matrix of the LDPC code, the LDPC code including information bits and parity bits, the parity check matrix including an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits, the information matrix part being represented by a parity check matrix initial value table, and the parity check matrix initial value table being a table indicating a position of an element 1 of the information matrix part for each 360 columns as   
       5 519 825 1871 2098 2478 2659 2820 3200 3294 3650 3804 3949 4426 4460 4503 4568 4590 4949 5219 5662 5738 5905 5911 6160 6404 6637 6708 6737 6814 7263 7412 
       81 391 1272 1633 2062 2882 3443 3503 3535 3908 4033 4163 4490 4929 5262 5399 5576 5768 5910 6331 6430 6844 6867 7201 7274 7290 7343 7350 7378 7387 7440 7554 
       105 975 3421 3480 4120 4444 5957 5971 6119 6617 6761 6810 7067 7353 
       6 138 485 1444 1512 2615 2990 3109 5604 6435 6513 6632 6704 7507 
       20 858 1051 2539 3049 5162 5308 6158 6391 6604 6744 
       7071 7195 7238 
       1140 5838 6203 6748 
       6282 6466 6481 6638 
       2346 2592 5436 7487 
       2219 3897 5896 7528 
       2897 6028 7018 
       1285 1863 5324 
       3075 6005 6466 
       5 6020 7551 
       2121 3751 7507 
       4027 5488 7542 
       2 6012 7011 
       3823 5531 5687 
       1379 2262 5297 
       1882 7498 7551 
       3749 4806 7227 
       2 2074 6898 
       17 616 7482 
       9 6823 7480 
       5195 5880 7559. 
     
     
         9 . The data processing device according to  claim 8 , wherein
 if a row of the parity check matrix initial table is represented by i and a parity length of the LDPC code is represented by M, the 2+360×(i−1)-th column of the parity check matrix is obtained by the cyclic shift of the 1+360×(i−1)-th column of the parity check matrix indicating a position of an element 1 in the parity check matrix initial value table downward by q=M/360.   
     
     
         10 . The data processing device according to  claim 8 , wherein
 as for the 1+360×(i−1)-th column of the parity check matrix,   an i-th row of the parity check matrix initial value table represents the row number of the element 1 of the 1+360×(i−1)-th column of the parity check matrix, and   as for each column from the 2+360×(i−1)-th column to a 360×i-th column being the column other than the 1+360×(i−1)-th column of the parity check matrix,   if an i-th row j-th column value of the parity check matrix initial value table is represented as h i, j  and the row number of a j-th element 1 of a w-th column of the parity check matrix H is represented as H w-j ,   a row number H w-j  of the element 1 of the w-th column being the column other than the 1+360×(i−1)-th column of the parity check matrix is represented by the equation H w-j =mod {h i,j +mod((w−1), 360)×M/360, M).   
     
     
         11 . The data processing device according to  claim 8 , wherein
 the parity check matrix has no cycle-4.   
     
     
         12 . The data processing device according to  claim 8 , wherein
 the parity check matrix of the LDPC code belongs to an ensemble in which the performance threshold being Eb/No at which a BER starts to decrease is a predetermined value or smaller is found by multi-edge type density evolution.   
     
     
         13 . A data processing method, comprising:
 a step of decoding, which decodes an LDPC (low density parity check) code provided from data transmitted from a transmitting device, which includes an encoder, which encodes information bits into an LDPC (low density parity check) code whose code length is 16200 bits and code rate is 8/15 based on a parity check matrix of the LDPC code, the LDPC code including information bits and parity bits, the parity check matrix including an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits, the information matrix part being represented by a parity check matrix initial value table, and the parity check matrix initial value table being a table indicating a position of an element 1 of the information matrix part for each 360 columns as   
       5 519 825 1871 2098 2478 2659 2820 3200 3294 3650 3804 3949 4426 4460 4503 4568 4590 4949 5219 5662 5738 5905 5911 6160 6404 6637 6708 6737 6814 7263 7412 
       81 391 1272 1633 2062 2882 3443 3503 3535 3908 4033 4163 4490 4929 5262 5399 5576 5768 5910 6331 6430 6844 6867 7201 7274 7290 7343 7350 7378 7387 7440 7554 
       105 975 3421 3480 4120 4444 5957 5971 6119 6617 6761 6810 7067 7353 
       6 138 485 1444 1512 2615 2990 3109 5604 6435 6513 6632 6704 7507 
       20 858 1051 2539 3049 5162 5308 6158 6391 6604 6744 7071 7195 7238 
       1140 5838 6203 6748 
       6282 6466 6481 6638 
       2346 2592 5436 7487 
       2219 3897 5896 7528 
       2897 6028 7018 
       1285 1863 5324 
       3075 6005 6466 
       5 6020 7551 
       2121 3751 7507 
       4027 5488 7542 
       2 6012 7011 
       3823 5531 5687 
       1379 2262 5297 
       1882 7498 7551 
       3749 4806 7227 
       2 2074 6898 
       17 616 7482 
       9 6823 7480 
       5195 5880 7559.