Electrostatic discharge protection circuit and electrostatic discharge protection device

Abstract

The present invention provides an ESD protection circuit electrically connected between a high voltage power line and a low voltage power line, and the ESD protection circuit includes a bipolar junction transistor (BJT) and a trigger source. A collector of the BJT is electrically connected to the high voltage power line, and an emitter and a base of the BJT are electrically connected to the low voltage power line. The trigger source is electrically connected between the base of the BJT and the high voltage power line.

What is claimed is: 
     
         1 . An ESD protection circuit electrically connected between a high voltage power line and a low voltage power line, and the ESD protection circuit comprising:
 a bipolar junction transistor (BJT), wherein a collector of the BJT is electrically connected to the high voltage power line, and an emitter and a base of the BJT are electrically connected to the low voltage power line; and   a trigger source electrically connected between the base of the BJT and the high voltage power line.   
     
     
         2 . The ESD protection circuit according to  claim 1 , further comprising a resistor electrically connected between the base of the BJT and the low voltage power line. 
     
     
         3 . The ESD protection circuit according to  claim 1 , wherein the trigger source comprises an NMOS transistor, wherein a drain of the NMOS transistor is electrically connected to the high voltage power line, and a gate and a source of the NMOS transistor are electrically connected to the base of the BJT. 
     
     
         4 . The ESD protection circuit according to  claim 1 , wherein the trigger source comprises an NMOS transistor, a capacitor and a resistor, wherein a drain and a source of the NMOS transistor are electrically connected to the high voltage power line and the base of the BJT respectively, the capacitor is electrically connected between the drain and a gate of the NMOS transistor, and the resistor is electrically connected between the gate and the source of the NMOS transistor. 
     
     
         5 . The ESD protection circuit according to  claim 1 , wherein the trigger source comprises an NMOS transistor, a capacitor, a resistor and an inverter, wherein a drain and a source of the NMOS transistor are electrically connected to the high voltage power line and the base of the BJT respectively, a gate of the NMOS transistor is electrically connected to an output node of the inverter, the resistor is electrically connected between an input node of the inverter and the drain of the NMOS transistor, and the capacitor is electrically connected between the input node of the inverter and the source of the NMOS transistor. 
     
     
         6 . The ESD protection circuit according to  claim 1 , wherein the trigger source comprises a PMOS transistor, a capacitor and a resistor, wherein a source and a drain of the PMOS transistor are electrically connected to the high voltage power line and the base of the BJT respectively, the capacitor is electrically connected between a gate of the PMOS transistor, and the resistor is electrically connected between the gate and the source of the PMOS transistor. 
     
     
         7 . The ESD protection circuit according to  claim 1 , wherein the trigger source comprises a PMOS transistor, a capacitor, a resistor and an inverter, wherein a source and a drain of the PMOS transistor are electrically connected to the high voltage power line and the base of the BJT respectively, a gate of the PMOS transistor is electrically connected to an output node of the inverter, the capacitor is electrically connected between the source of the PMOS transistor and an input node of the inverter, and the resistor is electrically connected between the input node of the inverter and the drain of the PMOS transistor. 
     
     
         8 . The ESD protection circuit according to  claim 1 , wherein the trigger source comprises an NPN BJT, wherein a base and an emitter of the NPN BJT are electrically connected to the base of the BJT, and a collector of the NPN BJT is electrically connected to the high voltage power line. 
     
     
         9 . The ESD protection circuit according to  claim 1 , wherein the trigger source comprises a PNP BJT, wherein a base and an emitter of the PNP BJT are electrically connected to the high voltage power line, and a collector of the PNP BJT is electrically connected to the base of the BJT. 
     
     
         10 . The ESD protection circuit according to  claim 1 , wherein the BJT is an NPN BJT. 
     
     
         11 . An ESD protection circuit connected between a high voltage power line and a low voltage power line, and the ESD protection circuit comprising:
 a first BJT comprising a first parasitic diode; and   a second BJT comprising a second parasitic diode, wherein a collector of the first BJT and a collector of the second BJT are electrically connected to the high voltage power line, and an emitter and a base of the first BJT and an emitter and a base of the second BJT are electrically connected to the low voltage power line.   
     
     
         12 . The ESD protection circuit according  claim 11 , wherein a breakdown voltage of the first parasitic diode is lower than a breakdown voltage of the second parasitic diode. 
     
     
         13 . The ESD protection circuit according  claim 11 , wherein the first BJT has a first base width, the second BJT has a second base width, and the first base width is shorter than the second base width. 
     
     
         14 . The ESD protection circuit according  claim 11 , further comprising a resistor connected between the base of the first BJT and the low voltage power line. 
     
     
         15 . An ESD protection device, comprising:
 a substrate;   a buried layer buried in the substrate, and the buried layer having a first conductive type;   a first well disposed in the substrate, and the first well being in contact with the buried layer and having the first conductive type;   a second well disposed in the substrate, and the second well being in contact with the buried layer and the first well and having a second conductive type;   a first doped region disposed in the second well, and the first doped region having the first conductive type; and   a second doped region disposed in the second well, and the second doped region having the second conductive type, wherein the second doped region is disposed between the first doped region and the first well.   
     
     
         16 . The ESD protection device according to  claim 15 , wherein a width of the second well between the first doped region and the first well is larger than a width of the second well between the first doped region and the buried layer. 
     
     
         17 . The ESD protection device according to  claim 15 , wherein a doping concentration of the buried layer is larger than a doping concentration of the first well. 
     
     
         18 . The ESD protection device according to  claim 15 , further comprising a third doped region disposed in the first well, and the third doped region having the first conductive type, wherein a doping concentration of the third doped region is larger than a doping concentration of the buried layer. 
     
     
         19 . The ESD protection device according to  claim 15 , wherein the first well comprises a plurality of wells. 
     
     
         20 . The ESD protection device according to  claim 15 , wherein the buried layer comprises at least one through hole. 
     
     
         21 . The ESD protection device according to  claim 15 , further comprises a graded region, and the graded region is disposed between the first doped region and the second well.