Finfet structures having uniform channel size and methods of fabrication

Abstract

Methods of fabricating circuit structures including FinFET structures are provided, including: providing a substrate and a first material having a first threshold voltage above the substrate, and a second material having a second threshold voltage lower than the first threshold voltage above the first material; forming fins having base fin portions formed from the first material and upper fin portions formed from the second material; providing gate structures over the fins to form one or more FinFET structures, wherein the gate structures wrap around at least the upper fin portions and have an operating voltage lower than the first threshold voltage and higher than the second threshold voltage, so that the upper fin portions define a channel size of the one or more FinFET structures. Circuit structures including FinFET structures are also provided, in which the FinFET structures have a uniform channel size defined only by upper fin portions thereof.

What is claimed is: 
     
         1 . (canceled) 
     
     
         2 . The method of  claim 21 , wherein at least one gate structure of the gate structures further contacts at least a portion of a respective at least one base fin portion of at least one FinFET structure, and wherein the operating voltage of the at least one gate structure being lower than the first threshold voltage of the first material facilitates preventing the at least one base fin portion from defining the channel size of the at least one FinFET structure. 
     
     
         3 . The method of  claim 21 , wherein the upper fin portions of the plurality of FinFET structures have a uniform height above the base fin portions so that the plurality of FinFET structures have a uniform channel size. 
     
     
         4 . (canceled) 
     
     
         5 . The method of  claim 21 , wherein forming the plurality of fins comprises disposing a first dielectric material between the plurality of fins, and wherein the method further comprises:
 removing at least a portion of the plurality of fins, the removing forming at least one trench in the substrate;   providing a second dielectric material disposed in the at least one trench in the substrate; and   recessing the first dielectric material and second dielectric material, prior to providing gate structures over the plurality of fins, to a depth sufficient to expose at least the outer surfaces of the upper fin portions.   
     
     
         6 . The method of  claim 21 , wherein the plurality of fins comprise a first threshold voltage defined in part by a first band-gap of the first material, and a second threshold voltage defined in part by a second band-gap of the second material, and wherein the second band-gap is selected to be smaller than the first band-gap. 
     
     
         7 . The method of  claim 21 , wherein forming a plurality of fins comprises the first material comprising implanting a dopant into at least a portion of the substrate to form at least one doped region, the base fin portions formed from the at least one doped region, and wherein providing the second material above the first material comprises providing a layer of the second material over the substrate and the at least one doped region. 
     
     
         8 . The method of  claim 7 , wherein the dopant is a first dopant having a conductivity type, and the method further comprises implanting a second dopant into the upper fin portions, the second dopant having a same conductivity type as the first dopant. 
     
     
         9 . The method of  claim 8 , wherein the base fin portions have a first dopant concentration, and wherein the upper fin portions have a second dopant concentration, the second dopant concentration differing from the first dopant concentration. 
     
     
         10 . The method of  claim 9 , wherein the first material has a first threshold voltage defined in part by the first dopant concentration, and the second material has second threshold voltage defined in part by the second dopant concentration, and wherein the second dopant concentration is selected to be lower than the first dopant concentration. 
     
     
         11 . The method of  claim 8 , wherein the dopant is a first dopant having a first conductivity type, the at least a portion of the substrate is a first portion of the substrate, the at least one doped region is a first doped region, and the base fin portions formed from the first doped region are first base fin portions, and the method further comprises providing a third material above the substrate by implanting a third dopant into a second portion of the substrate to form a second doped region, wherein second base fin portions are formed from the second doped region, and wherein providing the second material further comprises providing a layer of the second material over the substrate and the first doped region and the second doped region. 
     
     
         12 . The method of  claim 11 , wherein conductivity type of the first and second dopant is a first conductivity type, and wherein the third dopant has a second conductivity type, the second conductivity type being different from the first conductivity type. 
     
     
         13 . The method of  claim 12 , wherein the upper fin portions over the first base fin portions are first upper fin portions, and the method further comprises implanting a fourth dopant into second upper fin portions over the second base fin portions, the fourth dopant having the same conductivity type as the third dopant. 
     
     
         14 . The method of  claim 13 , wherein the second base fin portions have a third dopant concentration of the third dopant, and wherein the second upper fin portions have a fourth dopant concentration of the fourth dopant, the fourth dopant concentration differing from the third dopant concentration. 
     
     
         15 . The method of  claim 14 , further comprising a third threshold voltage defined in part by the third dopant concentration of the second base fin portions, a fourth threshold voltage defined in part by the fourth dopant concentration of the second upper fin portions, and wherein the fourth dopant concentration is selected to be lower than the third dopant concentration so that the operating voltage of the gate structures is higher than the fourth threshold voltage and lower than the third threshold voltage. 
     
     
         16 . (canceled) 
     
     
         17 . The structure of  claim 22 , wherein the first material has a first threshold voltage defined in part by a first band-gap between a valence band and conduction band of the first material, and the second material has a second threshold voltage defined in part by a second band-gap between a valence band and a conduction band of the second material, and wherein the second band-gap is larger than the first band-gap. 
     
     
         18 . The structure of  claim 21 , wherein the upper fin portions of the one or more FinFET structures have a uniform height above the base fin portions so that the one or more FinFET structures have a uniform channel size. 
     
     
         19 . The structure of  claim 22 , wherein at least one gate structure of the gate structures further contacts at least a portion of a respective at least one base fin portion of at least one FinFET structure, and wherein the operating voltage of the at least one gate structure being lower than the first threshold voltage of the first material facilitates preventing the at least one base fin from defining the channel size of the at least one FinFET structure. 
     
     
         20 . The structure of  claim 22 , wherein the first material comprises a first dopant and the second material comprises a second dopant, the first dopant and the second dopant having a same conductivity type, and wherein the base fin portions have a first dopant concentration of the first dopant and the upper fin portions have a second dopant concentration of the second dopant, the second dopant concentration being lower than the first dopant concentration. 
     
     
         21 . A method comprising:
 providing a substrate for a semiconductor device;   forming a plurality of fins above the substrate, the fins having an upper portion comprising a first material and a lower portion comprising a second material different from the first material, the first and second materials be selected to allow only the upper portions of the fins to function as a channel;   providing a dielectric material, wherein the lower portion of said plurality of fins is located at least partially below the dielectric material and the upper portions of said fins are located completely above the dielectric material; and   forming a plurality of gates over said plurality of fins, said plurality of gates having varying heights on opposite sides of a fin of said plurality of fins to facilitate the plurality of fins have uniform channel heights within a plurality of FinFET structures.   
     
     
         22 . A structure comprising:
 a substrate for a semiconductor device;   a plurality of fins above the substrate, the fins having an upper portion comprising a first material and a lower portion comprising a second material different from the first material, the first and second materials be selected to allow only the upper portions of the fins to function as a channel;   a dielectric material, wherein the lower portion of said plurality of fins is located at least partially below the dielectric material and the upper portions of said fins are located completely above the dielectric material; and   a plurality of gates over said plurality of fins, said plurality of gates having varying heights on opposite sides of a fin of said plurality of fins to facilitate the plurality of fins have uniform channel heights within a plurality of FinFET structures.