Devices with fully and partially silicided gate structures in gate first cmos technologies

Abstract

A semiconductor product with certain devices having a first device with a fully silicided (FuSi) gate and a second device with a partially silicided gate is disclosed. In one example, the first semiconductor device is recessed, resulting in a recessed first gate electrode material which is fully silicided during a subsequent silicidation process. On the gate electrode material of the second semiconductor device, a silicide portion is formed above a layer of polysilicon or amorphous silicon during the silicidation process.

What is claimed: 
     
         1 . A semiconductor device structure, comprising:
 a first semiconductor device with a first active region formed in a semiconductor substrate and a first gate structure disposed over the first active region, the first gate structure having a fully silicided gate electrode; and   a second semiconductor device with a second active region formed in the semiconductor substrate and a second gate structure disposed over the second active region, the second gate structure having a partially silicided gate electrode.   
     
     
         2 . The semiconductor device structure of  claim 1 , further comprising strain-inducing material portions formed within the first active region in alignment with the first gate structure. 
     
     
         3 . The semiconductor device structure of  claim 1 , wherein the first gate structure comprises a gate dielectric, a work function adjusting material disposed on the gate dielectric, and a first silicide contact disposed on the work function adjusting material. 
     
     
         4 . The semiconductor device structure of  claim 1 , wherein the second gate structure comprises a gate dielectric, a work function adjusting material disposed on the gate dielectric, a gate electrode material formed by one of polysilicon and amorphous silicon, and a first silicide contact disposed on the gate electrode material. 
     
     
         5 . The semiconductor device structure of  claim 1 , wherein the first semiconductor device forms a PMOS device and the second semiconductor device forms an NMOS device. 
     
     
         6 . A semiconductor device structure, comprising:
 a first semiconductor device with a first active region formed in a semiconductor substrate and a first gate structure disposed over said first active region, said first gate structure comprising:
 a first portion of a gate dielectric layer; 
 a first work function adjusting layer positioned above said first portion of said gate dielectric layer; and 
 a first metal silicide layer positioned on and in contact with said first work function adjusting layer; and 
   a second semiconductor device with a second active region formed in said semiconductor substrate and a second gate structure disposed over said second active region, said second gate structure comprising:
 a second portion of said gate dielectric layer; 
 a second work function adjusting layer positioned above said second portion of said gate dielectric layer; 
 a layer of polysilicon or amorphous silicon positioned above said second work function adjusting layer; and 
 a second metal silicide layer positioned on and in contact with said layer of polysilicon or amorphous silicon. 
   
     
     
         7 . The semiconductor device structure of  claim 6 , further comprising strain-inducing material portions formed within said first active region in alignment with said first gate structure. 
     
     
         8 . The semiconductor device structure of  claim 7 , wherein said first semiconductor device forms a PMOS device and said second semiconductor device forms an NMOS device. 
     
     
         9 . The semiconductor device structure of  claim 6 , wherein said gate dielectric layer comprises one of hafnium oxide or hafnium silicon oxynitride. 
     
     
         10 . The semiconductor device structure of  claim 6 , wherein said first work function adjusting layer and said second work function adjusting layer are comprised of a same material. 
     
     
         11 . The semiconductor device structure of  claim 10 , wherein said first work function adjusting layer and said second work function adjusting layer comprise one of Al 2 O 3  or LaO. 
     
     
         12 . The semiconductor device structure of  claim 6 , wherein said first and second metal silicide layers comprise a same metal silicide material. 
     
     
         13 . The semiconductor device structure of  claim 12 , wherein said first and second metal silicide layers comprise nickel. 
     
     
         14 . The semiconductor device structure of  claim 6 , wherein said first work function adjusting layer is positioned on and in contact with said first portion of said gate dielectric layer and said second work function adjusting layer is positioned on and in contact with said second portion of said gate dielectric layer. 
     
     
         15 . A semiconductor device structure, comprising:
 a first semiconductor device with a first active region formed in a semiconductor substrate and a first gate structure disposed over said first active region, said first gate structure comprising:
 a first portion of a gate dielectric layer; 
 a first portion of a work function adjusting layer positioned on and in contact with said first portion of said gate dielectric layer; and 
 a first portion of a metal silicide layer positioned on and in contact with said first portion of said work function adjusting layer; and 
   a second semiconductor device with a second active region formed in said semiconductor substrate and a second gate structure disposed over said second active region, said second gate structure comprising:
 a second portion of said gate dielectric layer; 
 a second portion of said work function adjusting layer positioned on and in contact with said second portion of said gate dielectric layer; 
 a layer of polysilicon or amorphous silicon positioned on and in contact with said second portion of said work function adjusting layer; and 
 a second portion of said metal silicide layer positioned on and in contact with said layer of polysilicon or amorphous silicon. 
   
     
     
         16 . The semiconductor device structure of  claim 15 , wherein said first semiconductor device forms a PMOS device and said second semiconductor device forms an NMOS device. 
     
     
         17 . The semiconductor device structure of  claim 15 , wherein said gate dielectric layer comprises one of hafnium oxide or hafnium silicon oxynitride. 
     
     
         18 . The semiconductor device structure of  claim 17 , wherein said work function adjusting layer comprises one of Al 2 O 3  or LaO. 
     
     
         19 . The semiconductor device structure of  claim 18 , wherein said metal silicide layer comprises nickel.