Image sensor with a split-counter architecture

Abstract

A split-counter architecture is implemented within an image sensor system. A first counter within an image sensor region counts image data from pixel regions within the image sensor region, and outputs the most significant bits of the image data to a second counter external to the image sensor region, reducing the bandwidth required between the image sensor region and the second counter, and reducing the size of the counters within the image sensor region.

What is claimed is: 
     
         1 . An integrated-circuit image sensor comprising:
 an image sensor region comprising:
 an array of pixel regions, each pixel region including at least one photosensitive element for detecting light incident upon the pixel region; and 
 a plurality of local registers coupled to the pixel regions for storing K-bit values, each K-bit value indicative of the light detected by at least one of the photosensitive elements of a coupled pixel region, the K-bit values comprising K1 less significant bits and K2 more significant bits; 
   communication line groups, each communication line group selectably coupled to a plurality of the local registers and configurable to receive the K1 less significant bits and the K2 more significant bits from each of the selectably coupled local registers; and   a controller coupled to the image sensor region and configured to instruct the local registers to, for each pixel region:
 output the K2 more significant bits on the respective communication line group for that local register and reset the K2 more significant bits; and 
 output the K1 less significant bits on the respective communication line group for that local register and reset the K1 less significant bits, wherein the K2 more significant bits are output multiple times for each time the K1 less significant bits are output.