US2016197152A1PendingUtilityA1

Semiconductor component and method for producing it

Assignee: INFINEON TECHNOLOGIES AUSTRIAPriority: Jul 18, 2007Filed: Mar 14, 2016Published: Jul 7, 2016
Est. expiryJul 18, 2027(~1 yrs left)· nominal 20-yr term from priority
Inventors:Franz Hirler
H10P 50/691H10P 32/1408H10P 32/171H10W 10/051H10W 10/50H10D 64/519H10D 64/257H10D 64/256H10D 62/157H10D 62/106H10D 64/117H10D 64/112H10D 62/393H10D 62/127H10D 62/103H10D 30/0291H10D 30/65H10D 12/032H10D 8/01H10D 30/66H01L 29/1095H01L 29/66712H01L 29/66333H01L 29/404H01L 29/0696H01L 29/407H01L 21/2254H01L 21/308H01L 29/6609
52
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Claims

Abstract

A semiconductor component having differently structured cell regions, and a method for producing it. For this purpose, the semiconductor component includes a semiconductor body. A first electrode on the top side of the semiconductor body is electrically connected to a first zone near the surface of the semiconductor body. A second electrode is electrically connected to a second zone of the semiconductor body. Furthermore, the semiconductor body has a drift path region, which is arranged in the semiconductor body between the first electrode and the second electrode. A cell region of the semiconductor component is subdivided into a main cell region and an auxiliary cell region, wherein the breakdown voltage of the auxiliary cells is greater than the breakdown voltage of the main cells.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method for producing semiconductor components having a drift path and main cell region and auxiliary cell region, wherein the properties of the drift path with regard to the breakdown voltage in the main cell region differ from the properties of the drift path in the auxiliary cell region, the method comprising:
 patterning a semiconductor wafer composed of a monocrystalline semiconductor body with semiconductor component structures in semiconductor chip positions which have diode, MOSFET or IGBT structures with a lateral or vertical drift path for the main cell region and the auxiliary cell region;   introducing vertical trench structures into the drift path in the auxiliary cell region;   depositing an insulating layer on the trench walls of the trench structures; and   filling the trench structures with a conductive material to form field plates.   
     
     
         2 . The method of  claim 1 , wherein longer trench structures for field plates in the case of a lateral drift path are introduced in the auxiliary cell region than in the main cell region. 
     
     
         3 . The method of  claim 1 , wherein the drift path is doped more highly in the auxiliary cell region than in the main cell region. 
     
     
         4 . The method of  claim 1 , wherein the trenches for the field plates are introduced with smaller spacings in the main cell region than in the auxiliary cell region. 
     
     
         5 . The method of  claim 1 , wherein an oxide thickness profile that differs from the oxide thickness profile of the trench structure of the field plates in the main cell region is provided for the field plates in the auxiliary cell region. 
     
     
         6 . The method of  claim 1 , wherein deeper trench structures for field plates in the case of a vertical drift path are introduced in the auxiliary cell region than in the main cell region. 
     
     
         7 . The method of  claim 1 , wherein, in the auxiliary cell region, at least one of a p−-conducting discharge layer is implanted or diffused as a field plate discharge structure before the trench structure is introduced and a pt conducting strip arranged transversely with respect to the drift path is implanted or diffused as field plate discharge structure before the trench structure is introduced. 
     
     
         8 . The method of  claim 1 , wherein, before dopants are introduced, first a patterned masking layer is applied to the semiconductor wafer, which layer covers the surface regions of the semiconductor body that are not doped. 
     
     
         9 . The method of  claim 1 , wherein, for introducing dopants, a dopant-containing layer is deposited on the masking layer patterned with windows and an indiffusion of the dopants into the semiconductor wafer is subsequently carried out. 
     
     
         10 . The method of  claim 1 , wherein, before vertical trench structures are introduced into the drift path, a patterned masking layer is applied to the semiconductor wafer, which layer has windows in the regions of the field plates.

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