Thin-film transistor substrate

Abstract

A thin-film transistor (TFT) substrate including a first region including a semiconductor layer, a first etch barrier layer covering the semiconductor layer, a first contact hole and a second contact hole, which are formed through the first etch barrier layer, a source electrode, which is disposed on the first etch barrier layer and is electrically connected to the semiconductor layer via the first contact hole, a drain electrode, which is disposed on the first etch barrier layer to be isolated from the source electrode, is electrically connected to the semiconductor layer via the second contact hole and has a transparent conductive oxide layer and a metal layer, and a pixel electrode, which is disposed on the first etch barrier layer and includes the transparent conductive oxide layer.

1 . A thin-film transistor (TFT) substrate comprising a first region, the first region comprising:
 a gate wire;   a first gate insulating layer covering the gate wire;   a through-hole formed through the first gate insulating layer and positioned over a part of the gate wire;   a common electrode disposed on the first gate insulating layer and comprising first and second portions thereof which are isolated from each other, with the through-hole interposed therebetween;   a second gate insulating layer covering the common electrode, the first gate insulating layer, and the part of the gate wire over which the through-hole is positioned;   a semiconductor layer disposed on the second gate insulating layer;   a first etch barrier layer covering the semiconductor layer;   a first contact hole and a second contact hole, both of which are formed through the first etch barrier layer;   a source electrode disposed on the first etch barrier layer and electrically connected to the semiconductor layer via the first contact hole and comprising a transparent conductive oxide layer and a metal layer;   a drain electrode disposed on the first etch barrier layer and isolated from the source electrode, the drain electrode being electrically connected to the semiconductor layer via the second contact hole and comprising a transparent conductive oxide layer and a metal layer; and   a pixel electrode comprising the transparent conductive oxide layer, a first area of the pixel electrode being disposed on the first etch barrier layer and in the same layer as the transparent conductive oxide layer of the source electrode and the transparent conductive layer of the drain electrode.   
     
     
         2 . (canceled) 
     
     
         3 . The TFT substrate of  claim 1 , wherein the first region further comprises:
 a passivation layer covering the source electrode and the drain electrode; and   a through-hole formed through the passivation layer; and   a second area of the pixel electrode is disposed in the through-hole.   
     
     
         4 . The TFT substrate of  claim 1 , wherein the first area of the pixel electrode comprises at least one incision pattern. 
     
     
         5 . The TFT substrate of  claim 1 , further comprising a second region comprising:
 a gate wire;   a first gate insulating layer covering the gate wire;   a common electrode comprising first and second portions thereof which are disposed on the first gate insulating layer and isolated from each other;   a second gate insulating layer disposed on the first gate insulating layer and covering the common electrode;   a second etch barrier layer disposed on the second gate insulating layer;   a third contact hole formed through the first gate insulating layer, the second gate insulating layer, and the second etch barrier layer;   a data wire electrically connected to the gate wire via the third contact hole and insulated from the common electrode by the second gate insulating layer, and   a passivation layer covering the data wire.   
     
     
         6 . The TFT substrate of  claim 1 , further comprising a third region, the third region comprising:
 a gate wire;   a first gate insulating layer covering the gate wire;   a common electrode disposed on the first gate insulating layer and comprising first and second portions thereof which are isolated from each other;   a second gate insulating layer disposed on the first gate insulating layer and covering the common electrode;   a third etch barrier layer disposed on the second gate insulating layer;   a fourth contact hole formed through the first gate insulating layer, the second gate insulating layer, and the etch barrier layer;   a data wire electrically connected to the gate wire and the common electrode via the fourth contact hole; and   a passivation layer covering the data wire.   
     
     
         7 . The TFT substrate of  claim 5 , wherein:
 the data wire comprises a transparent conductive oxide layer and a metal layer disposed on the transparent conductive oxide layer; and   the transparent conductive oxide layer of the data wire contacts the gate wire via the third contact hole and is insulated from the common electrode by the second gate insulating layer.   
     
     
         8 . The TFT substrate of  claim 6 , wherein:
 the data wire comprises a transparent conductive oxide layer and a metal layer disposed on the transparent conductive oxide layer; and   the transparent conductive oxide layer of the data wire contacts the gate wire and the common electrode via the fourth contact hole.   
     
     
         9 . The TFT substrate of  claim 1 , wherein the first contact hole and the second contact hole are formed in an area overlapping the semiconductor layer. 
     
     
         10 . The TFT substrate of  claim 1 , wherein:
 the first etch barrier layer comprises a first height portion and a second height portion having a height less than that of the first height portion; and   the second height portion is disposed in an area overlapping the semiconductor layer and is closer to at least one of the first contact hole and the second contact hole than the first height portion.   
     
     
         11 . The TFT substrate of  claim 1 , wherein:
 the first gate insulating layer comprises a first height portion and a second height portion having a height less than the first height portion;   the second height portion is disposed closer to the through-hole than is the third first height portion;   the second gate insulating layer comprises a third height portion and a fourth height portion having a height greater than that of the third height portion;   the third height portion is disposed in an area overlapping the common electrode; and   the fourth height portion is disposed closer to the through-hole than is the third height portion.   
     
     
         12 . The TFT substrate of  claim 5 , wherein:
 the first gate insulating layer comprises a first height portion and a second height portion having a height less than that of the first height portion;   the second height portion is disposed closer to the third contact hole than is the first height portion;   the second gate insulating layer comprises a third height portion and a fourth height portion having a height greater than that of the third height portion;   the third height portion is disposed in an area overlapping the common electrode; and   the fourth height portion is disposed closer to the third contact hole than is the third height portion.   
     
     
         13 . The TFT substrate of  claim 6 , wherein:
 the first gate insulating layer comprises a first height portion and a second height portion having a height less than that of the first height portion;   the second height portion is disposed closer to the fourth contact hole than is the first height portion; and   the second gate insulating layer comprises a third height portion.   
     
     
         14 . A TFT substrate comprising:
 a gate wire;   a first gate insulating layer covering the gate wire;   a through-hole formed through the first gate insulating layer and positioned over a part of the gate wire;   a common electrode disposed on the first gate insulating layer and comprising first and second portions thereof which are isolated from each other, with the through-hole interposed therebetween:   a second gate insulating layer covering the common electrode, the first gate insulating layer, and the part of the gate wire over which the through-hole is positioned;   a semiconductor layer disposed on the second gate insulating layer;   an etch barrier layer covering the semiconductor layer;   a contact hole formed through the etch barrier layer;   a data wire disposed directly on the etch barrier layer; and   a first region comprising the etch barrier layer comprising a first height portion and a second height portion having a second height less than a first height of the first height portion, the second height portion being disposed in an area overlapping the semiconductor layer to be closer to the contact hole than the first height portion; and   a second region comprising the etch barrier layer having a third height portion greater than the second height portion, wherein:   in the first region, the data wire is electrically connected to the semiconductor layer via the contact hole; and   in the second region, the data wire is insulated from a common electrode and is electrically connected to a gate wire via the contact hole.   
     
     
         15 . The TFT substrate of  claim 14 , further comprising a third region comprising the etch barrier layer comprising a fourth height portion having a height greater than that of the second height portion. 
     
     
         16 . (canceled) 
     
     
         17 . The TFT substrate of  claim 14 , further comprising a third region in which the data wire is electrically connected to the gate wire and the common electrode via the contact hole. 
     
     
         18 . (canceled)