High voltage lateral double-diffused metal oxide semiconductor field effect transistor (ldmosfet) having a deep fully depleted drain drift region

Abstract

Disclosed are semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.

What is claimed is: 
     
         1 . A semiconductor structure comprising:
 a semiconductor substrate having a top surface and a first type conductivity;   a transistor on said semiconductor substrate, said transistor comprising:
 a first intra-transistor well in said semiconductor substrate and having a second type conductivity; 
 a second intra-transistor well in said semiconductor substrate within said first intra-transistor well and having said first type conductivity, said first intra-transistor well extending deeper into said semiconductor substrate than said second intra-transistor well; 
 a third intra-transistor well in said semiconductor substrate, positioned laterally adjacent to said first intra-transistor well and having said first type conductivity, said first intra-transistor well and said third intra-transistor well extending a same depth into said semiconductor substrate; 
 a drain region within said first intra-transistor well at said top surface of said semiconductor substrate; and, 
 a source region within said third intra-transistor well at said top surface of said semiconductor substrate, said drain region and said source region having said second type conductivity; 
   a first isolation band in said semiconductor substrate below and in contact with said first intra-transistor well, said first isolation band having said first type conductivity;   a first isolation well positioned laterally around said transistor and having said second type conductivity;   a second isolation well positioned laterally between said first intra-transistor well and said first isolation well and extending vertically to said first isolation band, said second isolation well having said first type conductivity; and   a second isolation band in said semiconductor substrate and having said second type conductivity, said second isolation band being below said first isolation well, said first isolation band and said second intra-transistor well such that said transistor is electrically isolated from a lower portion of said semiconductor substrate,   said first intra-transistor well having a drain drift region between said second intra-transistor well and said first isolation band.   
     
     
         2 . The semiconductor structure of  claim 1 , said drain drift region being fully depleted. 
     
     
         3 . The semiconductor structure of  claim 1 , further comprising a gate structure on said top surface closer to said source region than said drain region, said gate structure having a first side above said first intra-transistor well and a second side above said third intra-transistor well. 
     
     
         4 . The semiconductor structure of  claim 1 , said third intra-transistor well being immediately adjacent to said first intra-transistor well. 
     
     
         5 . The semiconductor structure of  claim 1 , said third intra-transistor well being physically separated from said first intra-transistor well. 
     
     
         6 . The semiconductor structure of  claim 1 , further comprising a contact region within said second intra-transistor well at said top surface of said semiconductor substrate, said contact region having said first type conductivity. 
     
     
         7 . The semiconductor structure of  claim 1 , said transistor comprising a N-type transistor and said semiconductor structure further comprising a P-type transistor on said semiconductor substrate positioned laterally adjacent to said first isolation well, said second isolation band extending laterally below said P-type transistor. 
     
     
         8 . A semiconductor structure comprising:
 a semiconductor substrate having a top surface and a first type conductivity;   a transistor on said semiconductor substrate, said transistor comprising:
 a first intra-transistor well in said semiconductor substrate and having a second type conductivity; 
 a second intra-transistor well in said semiconductor substrate within said first intra-transistor well and having said first type conductivity, said first intra-transistor well extending deeper into said semiconductor substrate than said second intra-transistor well; 
 a third intra-transistor well in said semiconductor substrate, positioned laterally adjacent to said first intra-transistor well and having said first type conductivity, said first intra-transistor well and said third intra-transistor well being physically separated and extending a same depth into said semiconductor substrate; 
 a drain region within said first intra-transistor well at said top surface of said semiconductor substrate; and, 
 a source region within said third intra-transistor well at said top surface of said semiconductor substrate, said drain region and said source region having said second type conductivity; 
   a first isolation band in said semiconductor substrate below and in contact with said first intra-transistor well, said first isolation band having said first type conductivity;   a first isolation well positioned laterally around said transistor and having said second type conductivity;   a second isolation well positioned laterally between said first intra-transistor well and said first isolation well and extending vertically to said first isolation band, said second isolation well having said first type conductivity; and   a second isolation band in said semiconductor substrate and having said second type conductivity, said second isolation band being below said first isolation well, said first isolation band and said second intra-transistor well such that said transistor is electrically isolated from a lower portion of said semiconductor substrate,   said first intra-transistor well having a drain drift region between said second intra-transistor well and said first isolation band.   
     
     
         9 . The semiconductor structure of  claim 8 , said drain drift region being fully depleted. 
     
     
         10 . The semiconductor structure of  claim 8 , further comprising a gate structure on said top surface closer to said source region than said drain region, said gate structure having a first side above said first intra-transistor well and a second side above said third intra-transistor well. 
     
     
         11 . The semiconductor structure of  claim 10 , said gate structure being aligned above a space between said first intra-transistor well and said third intra-transistor well, said space having a same conductivity type and level as a lower portion of said semiconductor substrate below said second isolation band. 
     
     
         12 . The semiconductor structure of  claim 8 , further comprising a contact region within said second intra-transistor well at said top surface of said semiconductor substrate, said contact region having said first type conductivity. 
     
     
         13 . The semiconductor structure of  claim 8 , said transistor comprising a N-type transistor and said semiconductor structure further comprising a P-type transistor on said semiconductor substrate positioned laterally adjacent to said first isolation well, said second isolation band extending laterally below said P-type transistor. 
     
     
         14 . A semiconductor structure comprising:
 a semiconductor substrate having a top surface and a first type conductivity;   a transistor on said semiconductor substrate, said transistor comprising:
 a first intra-transistor well in said semiconductor substrate and having a second type conductivity; 
 a second intra-transistor well in said semiconductor substrate, positioned laterally adjacent to said first intra-transistor well and having said first type conductivity, said first intra-transistor well and said second intra-transistor well extending a same depth into said semiconductor substrate; 
 a drain region within said first intra-transistor well at said top surface of said semiconductor substrate; 
 a source region within said second intra-transistor well at said top surface of said semiconductor substrate, said drain region and said source region having said second type conductivity; and, 
 a contact region within said first intra-transistor well at said top surface of said semiconductor substrate between said drain region and said second intra-transistor well, said contact region having said first type conductivity; 
   a first isolation band in said semiconductor substrate below and in contact with said first intra-transistor well, said first isolation band having said first type conductivity;   a first isolation well positioned laterally around said transistor and having said second type conductivity;   a second isolation well positioned laterally between said first intra-transistor well and said first isolation well and extending vertically to said first isolation band, said second isolation well having said first type conductivity; and   a second isolation band in said semiconductor substrate and having said second type conductivity, said second isolation band being below said first isolation well, said first isolation band and said second intra-transistor well such that said transistor is electrically isolated from a lower portion of said semiconductor substrate,   said first intra-transistor well having a drain drift region between said contact region and said first isolation band.   
     
     
         15 . The semiconductor structure of  claim 14 , said drain drift region being fully depleted. 
     
     
         16 . The semiconductor structure of  claim 14 , further comprising a gate structure on said top surface closer to said source region than said drain region, said gate structure having a first side above said first intra-transistor well and a second side above said second intra-transistor well. 
     
     
         17 . The semiconductor structure of  claim 14 , said first intra-transistor well being immediately adjacent to said second intra-transistor well. 
     
     
         18 . The semiconductor structure of  claim 14 , said first intra-transistor well being physically separated from said second intra-transistor well. 
     
     
         19 . The semiconductor structure of  claim 18 , further comprising a gate structure aligned above a space between said first intra-transistor and said second intra-transistor well, said space having a same conductivity type and level as a lower portion of said semiconductor substrate below said second isolation band. 
     
     
         20 . The semiconductor structure of  claim 14 , said transistor comprising an N-type transistor and said semiconductor structure further comprising a P-type transistor on said semiconductor substrate positioned laterally adjacent to said first isolation well, said second isolation band extending laterally below said P-type transistor.