US2016197050A1PendingUtilityA1

Manufacturing method of semiconductor device and semiconductor device

Assignee: RENESAS ELECTRONICS CORPPriority: May 14, 2014Filed: Mar 16, 2016Published: Jul 7, 2016
Est. expiryMay 14, 2034(~7.8 yrs left)· nominal 20-yr term from priority
H10P 74/273H10W 90/756H10W 90/754H10W 90/736H10W 90/734H10W 74/00H10W 72/07252H10W 72/5525H10W 72/5524H10W 72/5522H10W 72/5449H10W 72/5363H10W 72/01953H10W 72/952H10W 72/884H10W 72/552H10W 72/536H10W 72/221H10W 72/0198H10W 72/59H10W 72/075H10W 72/50H10W 72/015H10W 72/932H10W 72/019H10W 72/983H10W 72/923H10W 72/01571H10W 72/07511H10W 72/354H10P 74/207H01L 2224/04042H01L 2224/48257H01L 2924/01022H01L 22/32H01L 2924/15311H01L 24/03H01L 24/85H01L 24/05H01L 2924/01029H01L 24/43H01L 22/14H01L 2924/01074H01L 2224/03831H01L 24/48
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Claims

Abstract

A manufacturing method of a BGA, includes the steps of: providing a semiconductor chip having electrode pads; and removing a natural oxide film formed on the surface of each of the electrode pads. Further, a first film comprised of a conductive member is formed on the surface of the electrode pad exposed by removing the natural oxide film, a wire is connected with the first film, and part of the wire is brought into contact with the electrode pad to form an alloy layer at the interface between the wire and the electrode pad. The crystal structure of the first film is comprised of a body-centered cubic lattice or a hexagonal close-packed lattice. The cost of the semiconductor device can be reduced while the bonding reliability of wire bonding of the semiconductor device is ensured.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A manufacturing method of a semiconductor device, comprising the steps of:
 (a) removing a natural oxide film from a surface of an electrode pad on a semiconductor chip;   (b) after the step (a), forming a conductive pad-cover film over the surface of the electrode pad exposed by removing the natural oxide film; and   (c) after the step (b), connecting a wire to the conductive pad-cover film, wherein   the step (c) includes braking the conductive pad-cover film and forming an alloy layer at the interface between the wire and the electrode pad to connect the wire with the electrode pad.   
     
     
         2 . The manufacturing method according to  claim 1 , wherein a crystal structure of the conductive pad-cover film is one of a body-centered cubic lattice and a hexagonal close-packed lattice. 
     
     
         3 . The manufacturing method according to  claim 1 , wherein the conductive pad-cover film contains chromium, titanium or tungsten. 
     
     
         4 . The manufacturing method according to  claim 1 , wherein
 the step (a) includes removing the natural oxide film in a vacuum atmosphere, and   the step (b) includes maintaining the vacuum atmosphere of step (a), in which the conductive pad-cover film is formed.   
     
     
         5 . The manufacturing method according to  claim 4 , wherein the step (a) includes sputter etching to remove the natural oxide. 
     
     
         6 . The manufacturing method according to  claim 1 , wherein in the step (b), the conductive pad-cover film is formed over the entire surface of the electrode pad. 
     
     
         7 . The manufacturing method according to  claim 1 , wherein the wire contains copper. 
     
     
         8 . The manufacturing method according to  claim 7 , wherein
 the electrode pad contains aluminum, and   the wire contains the copper as a main component.   
     
     
         9 . The manufacturing method according to  claim 1 , further comprising, after the step (b), connecting a probe to the electrode pad to perform a conductive test, wherein
 the probe is connected to an area of the electrode pad to which no wire is connected.   
     
     
         10 . A semiconductor device comprising:
 a semiconductor chip including:
 a main surface, and 
 a plurality of electrode pads on the main surface; 
   a plurality of leads around the semiconductor chip; and   a plurality of wires electrically connecting the electrode pads with the leads, respectively, wherein   a plurality of conductive pad-cover films are formed on surfaces the plurality of electrode pads, respectively, and   the plurality of wires are directly connected with the plurality of electrode pads through broken areas of the conductive pad-cover films where the electrode pads are exposed, alloy layers being formed at interfaces between the plurality of wires and the plurality of electrode pads, respectively.   
     
     
         11 . The semiconductor device according to  claim 10 , wherein a crystal structure of each of the conductive pad-cover films is one of a body-centered cubic lattice and a hexagonal close-packed lattice. 
     
     
         12 . The semiconductor device according to  claim 10 , wherein the conductive pad-cover film contains chromium, titanium or tungsten. 
     
     
         13 . The semiconductor device according to  claim 10 , wherein the plurality of wires each contain copper. 
     
     
         14 . The semiconductor device according to  claim 10 , wherein
 the plurality of electrode pads each contain aluminum, and   the plurality of wires each contain the copper as a main component.   
     
     
         15 . The semiconductor device according to  claim 10 , wherein part of the plurality of electrode pads each have a probe mark created by a probe for a conductive test, the probe mark existing in an area to which no wire is connected.

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