US2016191420A1PendingUtilityA1

Mitigating traffic steering inefficiencies in distributed uncore fabric

Assignee: INTEL CORPPriority: Dec 27, 2014Filed: Dec 27, 2014Published: Jun 30, 2016
Est. expiryDec 27, 2034(~8.4 yrs left)· nominal 20-yr term from priority
H04L 49/25H04L 45/7453H04L 49/356H04L 49/109
41
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

In an example, selected portions of an uncore fabric of a system-on-a-chip (SoC) or other embedded system is divided into two independent pipelines. Each pipeline operates independently of the other pipeline, and each accesses only one-half of the system memory, such as even or odd addresses in an interleaved memory. The two pipelines do not reconverge until after memory values have been returned. However, the uncore fabric may still present a single, monolithic interface to requesting devices. This allows system designers to treat the uncore fabric as a “black box” without modifying existing designs. Each incoming address may be processed by a deterministic hash, assigned to one of the pipelines, processed through memory, and then passed to a credit return.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An apparatus, comprising:
 an uncore fabric comprising:
 a request interface to receive an addressed data access request from a requesting agent, wherein the data interface is to present a monolithic access request interface to the requesting agent; and 
 a selection logic to hash a target address of the addressed data access request and to assign the addressed data access request to exactly one of n channels according to the hash. 
   
     
     
         2 . The apparatus of  claim 1 , wherein the uncore fabric further comprises:
 a plurality of n first-in, first-out buffers, wherein each buffer is to communicatively couple to exactly one channel.   
     
     
         3 . The apparatus of  claim 2 , wherein n=2, and the hash is an odd/even hash. 
     
     
         4 . The apparatus of  claim 2 , wherein the uncore fabric further comprises:
 a shared resource medium comprising n pipelines, wherein each pipeline is to communicatively couple to exactly one buffer and to exactly one addressed data region, wherein each pipeline is exclusive of each other pipeline.   
     
     
         5 . The apparatus of  claim 1 , further comprising an aggregator to aggregate data returns and to return data to the requesting agent. 
     
     
         6 . The apparatus of  claim 1 , further comprising an ordering logic to order a plurality of data access requests to the uncore fabric. 
     
     
         7 . The apparatus of  claim 6 , wherein the ordering logic further comprises a credit return mechanism. 
     
     
         8 . The apparatus of  claim 7 , wherein the credit return mechanism is to advertise one credit only when it has a guaranteed return value from all n pipelines. 
     
     
         9 . The apparatus of  claim 7 , wherein the credit return mechanism is operable to return a credit for a pipeline that has more pending requests than every other pipeline and pops a request. 
     
     
         10 . The apparatus of  claim 7 , wherein the credit return mechanism is to return a credit for a pipeline that has fewer pending requests than any other pipeline and pushes a request. 
     
     
         11 . A system on a chip, comprising:
 a requesting agent;   an addressed data resource; and   an uncore fabric to communicatively couple the requesting agent to the addressed data resource, the uncore fabric comprising:
 a request interface to receive an addressed data access request from a requesting agent, wherein the data interface is to present a monolithic access request interface to the requesting agent; and 
 a selection logic to hash a target address of the addressed data access request and to assign the addressed data access request to exactly one of n channels according to the hash. 
   
     
     
         12 . The system on a chip of  claim 11 , wherein the uncore fabric further comprises:
 a plurality of n first-in, first-out buffers, wherein each buffer is to communicatively couple to exactly one channel.   
     
     
         13 . The system on a chip of  claim 12 , wherein n=2, and the hash is an odd/even hash. 
     
     
         14 . The system on a chip of  claim 12 , wherein the uncore fabric further comprises:
 a shared resource medium comprising n pipelines, wherein each pipeline is to communicatively couple to exactly one buffer and to exactly one addressed data region, wherein each pipeline is exclusive of each other pipeline.   
     
     
         15 . The system on a chip of any  claim 11 , further comprising an aggregator to aggregate data returns and to return data to the requesting agent. 
     
     
         16 . The system on a chip of  claim 11 , further comprising an ordering logic to order a plurality of data access requests to the uncore fabric. 
     
     
         17 . The system on a chip of  claim 16 , wherein the ordering logic further comprises a credit return mechanism. 
     
     
         18 . The system on a chip of  claim 17 , wherein the credit return mechanism is to advertise one credit only when it has a guaranteed return value from all n pipelines. 
     
     
         19 . A method, comprising:
 providing a monolithic access request interface to a requesting agent;   receiving an addressed data access request from the requesting agent to an addressed data resource; and   hashing a target address of the addressed data access request;   assigning the addressed data access request to exactly one of n channels of an uncore fabric according to the hash.   
     
     
         20 . The method of  claim 19 , wherein n=2, and wherein the hash is an odd/even hash.

Join the waitlist — get patent alerts

Track US2016191420A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.