Rotate-Mask-Merge and Deposit Field Instructions for Packet Processing

Abstract

In an embodiment of the invention, a method of performing a byte-rotate-merge on computer hardware is discussed. Byte-rotating is performed on first and second source operands and are byte-rotated by first and second rotation constants respectively. The first byte-rotate output and the second byte-rotate output are merged. Bytes from the first byte-rotate output are output to a byte-rotate-merge output when control bits from a byte-mask are logical ones. Bytes from the second byte-rotate output are output to a byte-rotate-merge output when control bits from the byte-mask are logical zeros.

What is claimed is: 
     
         1 . A method for performing a byte-rotate-merge instruction on computer hardware comprising:
 receiving a first source argument and a second source argument;   byte-rotating the first source argument by a number of bytes specified by a first rotation constant resulting in a first byte-rotate output;   byte-rotating the second source argument by a number of bytes specified by a second rotation constant resulting in a second byte-rotate output;   merging the first byte-rotate output with the second byte-rotate output creating a byte-rotate-merge output wherein the byte-rotate-merge output comprises a plurality of bytes wherein each byte of the plurality of bytes has a corresponding control bit from a byte mask;   selecting the first byte-rotate output for each byte in the byte-rotate-merge output when the corresponding control bit from the byte mask is a logical one;   selecting the second byte-rotate output for each byte in the byte-rotate-merge output when the corresponding control bit from the byte mask is a logical zero.   
     
     
         2 . The method of  claim 1  wherein the byte rotate mask is encoded as the number of output bytes sourced from the argument which supplies low order bytes. 
     
     
         3 . A method of performing a deposit-field instruction on computer hardware comprising:
 receiving a source argument and a background argument;   replacing a specified position in the background argument with a specified length from a specified position in the source argument wherein the replacement is determined by a first shift constant, a second shift constant and a third shift constant.   
     
     
         4 . The method of  claim 3  wherein the first shift constant specifies a source rotation, the second shift constant specifies a least significant bit boundary of the background argument modified by the source argument and a third shift constant species the most significant bit boundary of the background argument modified by the source argument. 
     
     
         5 . An apparatus for performing a byte-rotate-merge instruction on computer hardware comprising:
 a first rotating circuitry being operable to byte-rotate a first source argument by a number of bytes specified by a first rotation constant resulting in a first byte-rotate output;   a second rotating circuitry being operable to byte-rotate a second source argument by a number of bytes specified by a second rotation constant resulting in a first byte-rotate output;   a byte-mask wherein an output of the byte-mask is used to determine a byte-rotate-merge output;   a multiplexer that receives the first byte-rotate output and the second byte-rotate output and outputs the byte-rotate-merge output wherein the byte-rotate-merge output comprises a plurality of bytes wherein each byte of the plurality of bytes has a corresponding control bit from the byte-mask;   wherein bytes from the first byte-rotate output are presented on the byte-rotate-merge output when the output of a byte-mask is a logical one;   wherein bytes from the second byte-rotate output are presented on the byte-rotate-merge output when the output of a byte-mask is a logical zero.   
     
     
         6 . The apparatus of  claim 5  wherein the byte rotate mask is encoded as the number of output bytes sourced from the argument which supplies low order bytes. 
     
     
         7 . An apparatus for performing a deposit-field instruction on computer hardware comprising:
 a first rotating circuitry being operable to byte-rotate a source argument by a ROT argument wherein the ROT argument is equal to a destination position argument minus a source position argument;   a first thermometer that receives the source position argument;   a second thermometer that receives the destination position argument plus the length argument;   a AND gate that receives an output from the first thermometer and an output from the second thermometer;   a multiplexer that receives the output of the AND gate, the output of the first rotating circuitry and a background argument;   wherein an output of the first thermometer enables bits from the source position and higher to be presented on an output of the multiplexer;   wherein an output of the second thermometer enables bits from the destination position plus the length argument and lower to be presented on an output of the multiplexer.