Bipolar transistor with extrinsic base region and methods of fabrication

Abstract

The present disclosure relates to integrated circuit (IC) structures and methods of forming the same. An IC structure according to the present disclosure can include: a doped substrate region adjacent to an insulating region; a crystalline base structure including: an intrinsic base region located on and contacting the doped substrate region, the intrinsic base region having a first thickness; an extrinsic base region adjacent to the insulating region, wherein the extrinsic base region has a second thickness greater than the first thickness; a semiconductor layer located on the intrinsic base region of the crystalline base structure; and a doped semiconductor layer located on the semiconductor layer.

What is claimed is: 
     
         1 . An integrated circuit (IC) structure comprising:
 a doped substrate region adjacent to an insulating region;   a crystalline base structure including:
 an intrinsic base region located on and contacting the doped substrate region, the intrinsic base region having a first thickness; 
 an extrinsic base region adjacent to the insulating region, wherein the extrinsic base region has a second thickness greater than the first thickness; 
   a semiconductor layer located on the intrinsic base region of the crystalline base structure; and   a doped semiconductor layer located on the semiconductor layer.   
     
     
         2 . The IC structure of  claim 1 , wherein the insulating region comprises a pair of insulating regions adjacent to two locations of the doped substrate region, and the crystalline base structure includes a pair of extrinsic base regions having the second thickness, wherein each of the pair of extrinsic base regions is adjacent to a corresponding one of the pair of insulating regions. 
     
     
         3 . The IC structure of  claim 1 , wherein the crystalline base structure comprises monocrystalline silicon germanium (SiGe). 
     
     
         4 . The IC structure of  claim 1 , further comprising a spacer adjacent to the semiconductor layer and the doped semiconductor layer, wherein the spacer electrically insulates the semiconductor layer and the doped semiconductor layer from the extrinsic base region of the crystalline base structure. 
     
     
         5 . The IC structure of  claim 1 , wherein the doped substrate region comprises one of an emitter and a collector of a bipolar transistor, the doped semiconductor layer comprises the other of the emitter and the collector of the bipolar transistor, and the crystalline base structure comprises a base of the bipolar transistor. 
     
     
         6 . The IC structure of  claim 1 , further comprising a silicide contact located on one of the doped substrate and the extrinsic base region of the crystalline base structure. 
     
     
         7 . The IC structure of  claim 6 , wherein the silicide contact is located on the doped substrate, and the doped substrate further includes a sub-collector region adjacent to the silicide contact having a higher concentration of dopants than a collector region of the doped substrate adjacent to the crystalline base structure. 
     
     
         8 . The IC structure of  claim 1 , further comprising a dielectric material positioned within the insulating region. 
     
     
         9 . The IC structure of  claim 1 , wherein the insulating region includes a first surface area adjacent to the extrinsic base region of the crystalline base structure and an opposing second surface area adjacent to the doped substrate region, the first surface area being greater than the second surface area.