Method for fabricating lightly doped drain area, thin film transistor and array substrate

Abstract

Embodiments of the disclosure provide a method for fabricating a lightly doped drain area, a thin film transistor, and a thin film transistor array substrate. In an embodiment of the disclosure, a poly-silicon layer, a gate insulation layer, and a gate metal layer are formed in sequence on a substrate; the gate metal layer is patterned to form a gate electrode; the gate insulation layer is etched to form a stepped structure, wherein a width of the gate electrode is smaller than a width of the stepped structure, and an edge of the stepped structure is not covered by the gate electrode; and the poly-silicon layer is doped by an ion doping process using the gate electrode and the gate insulation layer with the stepped structure as a mask to form both a lightly doped area and a heavily doped area.

What is claimed is: 
     
         1 . A method for fabricating a lightly doped area, the method comprising:
 forming a poly-silicon layer, a gate insulation layer, and a gate metal layer in sequence on a substrate;   patterning the gate metal layer to form a gate electrode;   etching the gate insulation layer to form a stepped structure, wherein a width of the gate electrode is smaller than a width of the stepped structure, and an edge of the stepped structure is not covered by the gate electrode; and   doping the poly-silicon layer by a doping process using the gate electrode and the gate insulation layer with the stepped structure as a mask to form a lightly doped area and a heavily doped area.   
     
     
         2 . The method for fabricating a lightly doped area according to  claim 1 , wherein the patterning the gate metal layer to form the gate electrode comprises:
 applying photo-resist on the gate metal layer, exposing the photo-resist using a mask, and developing the photo-resist to form a preliminary gate electrode pattern;   etching the gate metal layer by a first etching process to form a preliminary gate electrode; and   etching the preliminary gate electrode by a second etching process to form the gate electrode while keeping the photo-resist on a surface of the preliminary gate electrode.   
     
     
         3 . The method for fabricating a lightly doped area according to  claim 1 , wherein the patterning the gate metal layer to form the gate electrode comprises:
 applying photo-resist on the gate metal layer, exposing the photo-resist using a mask, and developing the photo-resist to form a preliminary gate electrode pattern; and   etching the gate metal layer by a second etching process to form the gate electrode.   
     
     
         4 . The method for fabricating a lightly doped area according to  claim 2 , wherein the etching the gate insulation layer to form the stepped structure, wherein the width of the gate electrode is smaller than the width of the stepped structure, and the edge of the stepped structure is not covered by the gate electrode comprises:
 etching the gate insulation layer for a first time by the first etching process to form a preliminary stepped structure after the gate metal layer is etched by the first etching process to form the preliminary gate electrode.   
     
     
         5 . The method for fabricating a lightly doped area according to  claim 4 , wherein after the gate electrode is formed, the method further comprises:
 etching the gate insulation layer for a second time by the first etching process to form a final stepped structure.   
     
     
         6 . The method for fabricating a lightly doped area according to  claim 5 , wherein an etching rate of the first etching is higher than an etching rate of the second etching. 
     
     
         7 . The method for fabricating a lightly doped area according to  claim 2 , wherein the etching the gate insulation layer to form the stepped structure, wherein the width of the gate electrode is smaller than the width of the stepped structure, and the edge of the stepped structure is not covered by the gate electrode comprises:
 etching the gate insulation layer by the first etching process to form the stepped structure after the gate electrode is formed.   
     
     
         8 . The method for fabricating a lightly doped area according to  claim 2 , wherein the first etching process is a dry etching process, and the second etching process is a wet etching process. 
     
     
         9 . The method for fabricating a lightly doped area according to  claim 1 , wherein the gate insulation layer is made of silicon nitride or silicon oxide. 
     
     
         10 . The method for fabricating a lightly doped area according to  claim 1 , wherein a width of an area of the stepped structure not covered by the gate electrode is equal to an expected width of the lightly doped area. 
     
     
         11 . The method for fabricating a lightly doped area according to  claim 1 , wherein a thickness of an area of the gate insulation layer other than the stepped structure is smaller than 800 angstroms. 
     
     
         12 . The method for fabricating a lightly doped area according to  claim 2 , wherein before the poly-silicon layer is doped by the doping process using the gate electrode and the gate insulation layer with the stepped structure as the mask to form the lightly doped area and the heavily doped area, the method further comprises:
 removing the remaining photo-resist.   
     
     
         13 . The method for fabricating a lightly doped area according to  claim 1 , wherein the poly-silicon layer is an un-doped poly-silicon layer before the poly-silicon layer is doped by the doping process using the gate electrode and the gate insulation layer with the stepped structure as the mask to form the lightly doped area and the heavily doped area. 
     
     
         14 . The method for fabricating a lightly doped area according to  claim 3 , wherein the etching the gate insulation layer to form the stepped structure, wherein the width of the gate electrode is smaller than the width of the stepped structure, and the edge of the stepped structure is not covered by the gate electrode comprises:
 etching the gate insulation layer by a first etching process to form the stepped structure after the gate electrode is formed.   
     
     
         15 . The method for fabricating a lightly doped area according to  claim 3 , wherein the second etching process by a wet etching process. 
     
     
         16 . The method for fabricating a lightly doped area according to  claim 3 , wherein before the poly-silicon layer is doped by the doping process using the gate electrode and the gate insulation layer with the stepped structure as the mask to form the lightly doped area and the heavily doped area, the method further comprises:
 removing the remaining photo-resist.   
     
     
         17 . A thin film transistor, comprising the lightly doped area fabricated in the method for fabricating a lightly doped area according to  claim 1 , wherein the thin film transistor further comprises:
 a substrate, and a poly-silicon layer, a gate insulation layer with a stepped structure, a gate electrode formed in sequence on the substrate,   wherein a width of the gate electrode is smaller than a width of the stepped structure, and an edge of the stepped structure is not covered by the gate electrode; and   a width of the lightly doped area is equal to a width of an area of the stepped structure not covered by the gate electrode.   
     
     
         18 . A thin film transistor array substrate, comprising a plurality of the thin film transistors according to  claim 17 .