US2016190263A1PendingUtilityA1

Devices formed by performing a common etch patterning process to form gate and source/drain contact openings

Assignee: GLOBALFOUNDRIES INCPriority: Jun 11, 2014Filed: Feb 25, 2016Published: Jun 30, 2016
Est. expiryJun 11, 2034(~7.9 yrs left)· nominal 20-yr term from priority
H10D 64/013H10W 20/089H10W 20/069H10W 20/077H10W 20/075H10D 84/0186H10D 84/0172H10D 84/0158H10D 84/0135H10D 84/83H10D 84/038H10D 84/013H10D 62/116H10D 64/259H01L 29/41783
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Claims

Abstract

A device includes an isolation region that defines an active region in a semiconducting substrate and a gate structure, wherein the gate structure has an axial length in a long axis direction thereof such that a first portion of the gate structure is positioned above the active region and a second portion of the gate structure is positioned above the isolation region. Additionally, a gate cap layer is positioned above the gate structure, wherein a first portion of the gate cap layer that is positioned above the first portion of the gate structure is thicker than a second portion of the gate cap layer that is positioned above the second portion of the gate structure.

Claims

exact text as granted — not AI-modified
What is claimed: 
     
         1 . A device, comprising:
 an isolation region that defines an active region in a semiconducting substrate;   a gate structure, wherein said gate structure has an axial length in a long axis direction thereof such that a first portion of said gate structure is positioned above said active region and a second portion of said gate structure is positioned above said isolation region; and   a gate cap layer positioned above said gate structure, wherein a first portion of said gate cap layer that is positioned above said first portion of said gate structure is thicker than a second portion of said gate cap layer that is positioned above said second portion of said gate structure.   
     
     
         2 . The device of  claim 1 , wherein said first and second portions of said gate cap layer comprise silicon nitride. 
     
     
         3 . The device of  claim 1 , wherein said second portion of said gate cap layer has a thickness that is approximately 10-20% of a thickness of said first portion of said gate cap layer. 
     
     
         4 . The device of  claim 1 , wherein said first portion of said gate cap layer comprises a plurality of layers of material and said second portion of said gate cap layer is made of a subset of said plurality of layers of material. 
     
     
         5 . The device of  claim 1 , wherein said gate cap layer consists of a single layer of material. 
     
     
         6 . The device of  claim 1 , wherein, when viewed in cross-section taken through said gate cap layer in a direction parallel to said long axis of said gate structure, said gate cap layer has a stepped profile. 
     
     
         7 . The device of  claim 1 , further comprising a gate contact structure that extends through said second portion of said gate cap layer and conductively contacts said second portion of said gate structure. 
     
     
         8 . A device, comprising:
 an isolation region positioned in a semiconducting substrate, said isolation region surrounding and defining an active region of said semiconducting substrate;   a gate structure extending continuously from said active region to said isolation region, wherein a first gate structure portion of said gate structure is positioned above said active region and a second gate structure portion of said gate structure is positioned above said isolation region; and   a gate cap layer positioned above said gate structure and comprising a plurality of material layers, wherein a first gate cap portion of said gate cap layer is positioned above said first gate structure portion and has a first gate cap thickness, and wherein a second gate cap portion of said gate cap layer is positioned above said second gate structure portion and has a second gate cap thickness that is less than said first gate cap thickness.   
     
     
         9 . The device of  claim 8 , wherein said first gate cap portion has a greater number of material layers than said second gate cap portion. 
     
     
         10 . The device of  claim 8 , wherein said first gate cap portion comprises at least three material layers and said second gate cap portion consists of a single material layer. 
     
     
         11 . The device of  claim 8 , wherein at least one of said plurality of material layers comprising said gate cap layer extends continuously from said first gate cap portion to said second gate cap portion. 
     
     
         12 . The device of  claim 8 , wherein a first one of said plurality of material layers comprises silicon and nitrogen, and wherein a second one of said plurality of material layers comprises a high-k dielectric material having a dielectric constant that is greater than approximately 10. 
     
     
         13 . The device of  claim 8 , wherein said gate cap layer has a stepped profile when viewed in cross-section taken through said gate cap layer in a direction that is parallel to a long axis of said gate structure. 
     
     
         14 . The device of  claim 8 , further comprising a gate contact structure that extends through said second gate cap portion and conductively contacts said second gate structure portion. 
     
     
         15 . The device of  claim 8 , wherein said second gate structure portion is positioned above a first portion of said isolation region, said gate structure further comprising a third gate structure portion that is positioned above a second portion of said isolation region and extends continuously from said first gate structure portion positioned above said active region, wherein said gate cap layer comprises a third gate cap portion that is positioned above said third gate structure portion, said third gate cap portion having a third gate cap thickness that is less than said first gate cap thickness. 
     
     
         16 . A device, comprising:
 an isolation region positioned in a semiconducting substrate, said isolation region surrounding and defining an active region of said semiconducting substrate;   a gate structure extending continuously from a first portion of said isolation region across said active region to a second portion of said isolation region, said gate structure comprising:
 a first gate structure portion positioned above said first portion of said isolation region; 
 a second gate structure portion positioned above said second portion of said isolation region; and 
 a third gate structure portion positioned above said active region; and 
   a gate cap layer positioned above said gate structure, said gate cap layer comprising:
 a first gate cap portion positioned above said first gate structure portion and having a first gate cap thickness; 
 a second gate cap portion positioned above said second gate structure portion and having a second gate cap thickness; and 
 a third gate cap portion positioned above said third gate structure portion and having a third gate cap thickness that is greater than each of said first and second gate cap thicknesses. 
   
     
     
         17 . The device of  claim 16 , wherein said first and second gate cap thicknesses are approximately 10-20% of said third gate cap thickness. 
     
     
         18 . The device of  claim 16 , wherein said gate cap layer comprises a plurality of material layers, said third gate cap portion having a greater number of material layers than either of said first and second gate cap portions. 
     
     
         19 . The device of  claim 16 , wherein said gate cap layer consists of a single layer of material. 
     
     
         20 . The device of  claim 16 , wherein said gate cap layer has a stepped profile when viewed in cross-section taken through said gate cap layer in a direction that is parallel to a long axis of said gate structure.

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