Monolithically integrated rgb pixel array and z pixel array

Abstract

An apparatus is described that includes first and second pixels arrays integrated on a same semiconductor chip. The first pixel array contains visible light pixels and no Z pixels. The second pixel array contains Z pixels and no visible light pixels. The first and second pixel arrays do not overlap on said same semiconductor chip.

1 . An apparatus, comprising:
 first and second pixels arrays integrated on a same semiconductor chip, said first pixel array containing visible light pixels and no Z pixels, said second pixel array containing Z pixels and no visible light pixels, wherein said first and second pixel arrays do not overlap on said same semiconductor chip.   
     
     
         2 . The apparatus of  claim 1  wherein said semiconductor chip includes at least one of:
 pixel array circuitry coupled to said first pixel array; 
 pixel array circuitry coupled to said second pixel array; 
 
     
     
         3 . The apparatus of  claim 1  wherein said semiconductor chip includes at least one of:
 ADC circuitry coupled downstream from said first pixel array; 
 ADC circuitry coupled downstream from said second pixel array. 
 
     
     
         4 . The apparatus of  claim 1  wherein said semiconductor chip includes at least one of:
 timing and control circuitry of an image sensor that includes said first pixel array; 
 timing and control circuitry of an image sensor that includes said second pixel array. 
 
     
     
         5 . The apparatus of  claim 1  wherein said semiconductor chip includes:
 pixel array circuitry coupled to said first and second pixel arrays; 
 ADC circuitry coupled to said pixel array circuitry; 
 timing and control circuitry coupled to said ADC circuitry. 
 
     
     
         6 . The apparatus of  claim 1  wherein said semiconductor chip is stacked on a lower semiconductor chip. 
     
     
         7 . The apparatus of  claim 6  wherein said lower semiconductor chip contains at least one of:
 pixel array circuitry coupled to at least one of said first and second pixel arrays; 
 ADC circuitry coupled downstream from at least one of said first and second pixel arrays; 
 timing and control circuitry of an image sensor that includes at least one of said first and second pixel arrays. 
 
     
     
         8 . The apparatus of  claim 1  wherein said semiconductor chip is mounted on a semiconductor chip package substrate. 
     
     
         9 . The apparatus of  claim 1  wherein said visible light pixels are smaller than said Z pixels. 
     
     
         10 . The apparatus of  claim 1  wherein said first and second pixel arrays are of the same size. 
     
     
         11 . A method, comprising:
 receiving substantially only visible light within a first region of a semiconductor chip's surface area;   receiving substantially only infrared light within a second region of a semiconductor chip's surface area, where, the first and second regions are separated;   pixelating the visible light into multiple colors within a first multilayer structure of the semiconductor chip within the first region;   pixelating the infrared light within a second multilayer structure of the semiconductor chip within the second region;   generating first electronic signals that are representative of the pixelated visible light with the semiconductor chip's substrate within the first region;   generating second electronic signals that are representative of the pixelated infrared light with the semiconductor chip's substrate within the second region.   
     
     
         12 . The method of  claim 11  wherein the second electronic signals are time-of-flight measurement signals. 
     
     
         13 . The method of  claim 11  wherein the method further comprises performing analog-to-digital conversion of at least one of the first and second electronic signals on the semiconductor chip. 
     
     
         14 . The method of  claim 11  wherein the method further comprises processing digital samples from said analog-to-digital conversion with an image signal processor. 
     
     
         15 . The method of  claim 11  wherein the method is performed on a handheld electronic device. 
     
     
         16 . A computing system, comprising:
 an applications processor having a plurality of general purpose processing cores and a memory controller coupled to the plurality of processing cores;   a system memory coupled to the memory controller;   a camera system coupled to the applications processor, said camera system including first and second pixels arrays integrated on a same semiconductor chip, said first pixel array containing visible light pixels and no Z pixels, said second pixel array containing Z pixels and no visible light pixels, wherein said first and second pixel arrays do not overlap on said same semiconductor chip.   
     
     
         17 . The computing system of  claim 16  wherein said semiconductor chip includes at least one of:
 pixel array circuitry coupled to said first pixel array; 
 pixel array circuitry coupled to said second pixel array; 
 
     
     
         18 . The computing system of  claim 16  wherein said semiconductor chip includes at least one of:
 ADC circuitry coupled downstream from said first pixel array; 
 ADC circuitry coupled downstream from said second pixel array. 
 
     
     
         19 . The computing system of  claim 16  wherein said semiconductor chip includes at least one of:
 timing and control circuitry of an image sensor that includes said first pixel array; 
 timing and control circuitry of an image sensor that includes said second pixel array. 
 
     
     
         20 . The computing system of  claim 16  wherein said semiconductor chip includes:
 pixel array circuitry coupled to said first and second pixel arrays; 
 ADC circuitry coupled to said pixel array circuitry; 
 timing and control circuitry coupled to said ADC circuitry.