Field effect transistor with self-adjusting threshold voltage

Abstract

Methods for forming field effect transistors (FETs) with improved ON/OFF current ratios in addition to short charging times and the resulting devices are disclosed. Embodiments include forming a gate oxide layer above a channel region in a substrate, forming a partial self-adjusting threshold voltage layer above a drain-side end of the gate oxide layer, and forming a gate above the partial self-adjusting threshold voltage layer and the gate oxide layer.

What is claimed is: 
     
         1 . A method comprising:
 forming a gate oxide layer above a channel region in a substrate; and   forming a self-adjusting threshold voltage layer by:
 forming a dummy gate on the gate oxide layer; 
 forming an ILD surrounding the gate oxide layer and the dummy gate; 
 removing the dummy gate; 
 forming a cavity; and 
 depositing a self-adjusting threshold voltage material on side surfaces of the cavity. 
   
     
     
         2 . The method according to  claim 1 , further comprising:
 forming the self-adjusting threshold voltage layer above a source-side end and the drain-side end of the gate oxide layer.   
     
     
         3 . The method according to  claim 1 , further comprising:
 depositing a gate material on side surfaces of the cavity, leaving exposed a middle portion of the self-adjusting threshold voltage layer.   
     
     
         4 . The method according to  claim 3 , wherein the gate material is poly-Si or metal. 
     
     
         5 . The method according to  claim 3 , further comprising:
 masking the self-adjusting threshold voltage layer with a hardmask, exposing the middle portion of the self-adjusting threshold voltage layer, prior to removing the middle portion of the self-adjusting threshold voltage layer.   
     
     
         6 . The method according to  claim 5 , further comprising:
 removing at least a middle portion of the self-adjusting threshold voltage layer.   
     
     
         7 . The method according to  claim 1 , comprising forming the self-adjusting threshold voltage layer to a thickness of 1 to 10 nm. 
     
     
         8 . The method according to  claim 7 , comprising forming the self-adjusting threshold voltage layer to a width of 5 to 20% a width of the gate oxide layer. 
     
     
         9 . The method according to  claim 8 , wherein the self-adjusting threshold voltage layer is formed of at least one of a dielectric material and a ferroelectric material. 
     
     
         10 . The method according to  claim 8 , wherein the self-adjusting threshold voltage layer is formed of silicon nitride (SiN). 
     
     
         11 . The method according to  claim 1 , comprising conformally depositing the self-adjusting threshold voltage layer on the sides and bottom surfaces of the cavity. 
     
     
         12 . The method according to  claim 1 , comprising forming the gate oxide layer of SiO 2  to a thickness of 25 to 100 nm. 
     
     
         13 . A method comprising:
 forming a gate oxide layer above a channel region in a substrate;   forming a gate above the gate oxide layer;   forming an inter-layer dielectric (ILD) surrounding the gate oxide layer and the gate;   removing a portion of the gate exposing a portion of the gate oxide layer and forming a cavity between the ILD, the gate oxide layer, and remaining gate;   forming a partial self-adjusting threshold voltage layer above the exposed portion of the gate oxide layer; and   forming a field plate in a remainder of the cavity.   
     
     
         14 . The method according to  claim 13 , comprising:
 conformally depositing the partial self-adjusting threshold voltage layer on side and bottom surfaces of the cavity.   
     
     
         15 . The method according to  claim 13 , comprising:
 forming the partial self-adjusting threshold voltage layer to a thickness of 1 to 10 nm.   
     
     
         16 . The method according to  claim 13 , comprising:
 removing 10 to 30% horizontally of the gate down to the gate oxide layer, forming the cavity.   
     
     
         17 . A device comprising:
 a substrate;   a channel region within the substrate;   a gate oxide layer above the channel region;   a gate above a first portion of the gate oxide layer, leaving exposed a second portion of the gate oxide layer;   a partial self-adjusting threshold voltage layer above the second portion of the gate oxide layer;   a field plate above the partial self-adjusting threshold voltage layer; and   an inter-layer dielectric (ILD) surrounding the gate oxide layer, the gate, the partial self-adjusting threshold voltage layer, and the field plate.   
     
     
         18 . The device according to  claim 17 , comprising:
 the partial self-adjusting threshold voltage layer conformally lining a cavity formed between the gate, the gate oxide layer, and the ILD.   
     
     
         19 . The device according to  claim 17 , comprising:
 the partial self-adjusting threshold voltage layer formed to a thickness of 1 to 10 nm.   
     
     
         20 . The device according to  claim 17 , comprising:
 the partial self-adjusting threshold voltage layer over 10 to 30% of a surface of the gate and the partial self-adjusting threshold voltage layer.