Reliable passivation layers for semiconductor devices

Abstract

Device and method for forming a device are disclosed. A substrate which is prepared with a dielectric layer having a top metal level of the device is provided. The top metal level includes top level conductive lines. A top dielectric layer which includes top via openings in communication with the top level conductive lines is formed over the top metal level. A patterned top conductive layer is formed on the top dielectric layer. The patterned top conductive layer includes a top via in the top via opening and a top conductive line. A first passivation sub-layer is formed to line the patterned conductive layer and exposed top dielectric layer. A plasma treatment is performed on the surface of the first passivation sub-layer to form a nitrided layer. A second passivation sub-layer is formed to line the nitrided layer. The plasma treatment improves the passivation integrity of the passivation stack.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a substrate prepared with atop dielectric layer, the top dielectric layer includes top via openings;   a patterned top conductive layer disposed on the top dielectric layer, the patterned top conductive layer includes a top via in the top via opening and a top conductive line, wherein the patterned top conductive layer exposes portions of the top dielectric layer; and   a passivation stack comprising
 a first oxide passivation sub-layer which lines the patterned top conductive layer and exposed portions of the top dielectric layer, wherein a top portion of the first oxide passivation sub-layer includes a nitrided layer, and 
 a second nitride passivation sub-layer disposed directly on the first passivation sub-layer; wherein the second nitride passivation sub-layer contacts the nitrided layer, the nitrided layer is separate and distinct from the second nitride passivation sub-layer. 
   
     
     
         2 . The device of  claim 1  comprising an intermediate dielectric layer separating the substrate and the top dielectric layer, the intermediate dielectric layer includes a top metal level of the device, wherein the top metal level includes top level conductive lines which are in communication with the patterned top conductive layer. 
     
     
         3 . The device of  claim 2  wherein the top level conductive lines comprise Cu or Cu alloy and the patterned top conductive layer comprises Al. 
     
     
         4 . The device of  claim 1  wherein the nitrided layer includes a different composition than the second nitride passivation sub-layer, the nitrided layer improves the integrity of the passivation stack. 
     
     
         5 . The device of  claim 4  wherein the first oxide passivation sub-layer comprises silicon oxide or doped silicon oxide and the second nitride passivation sub-layer comprises silicon nitride. 
     
     
         6 . The device of  claim 4  wherein the nitrided layer includes silicon nitride or silicon oxynitride. 
     
     
         7 . The device of  claim 1  wherein the thickness of the first oxide passivation sub-layer is about 6,000-14,000 Å and the thickness of the second nitride passivation sub-layer is about 4,000-10,000 Å. 
     
     
         8 . The device of  claim 1  wherein the patterned top conductive layer comprises a void above the top via and serves as an external contact of the semiconductor device for coupling to an external substrate. 
     
     
         9 . The device of  claim 1  wherein the top via openings are spaced about 2-3 μm apart and include sides of about 2-3 μm in length. 
     
     
         10 . A semiconductor device comprising:
 a substrate prepared with a top dielectric layer, the top dielectric layer includes top via openings;   a patterned top conductive layer disposed on the top dielectric layer, the patterned top conductive layer includes a top via in the top via opening and a top conductive line, wherein the patterned top conductive layer exposes portions of the top dielectric layer; and   a passivation stack comprising
 a first passivation sub-layer which lines the patterned top conductive layer and exposed portions of the top dielectric layer, 
 a second passivation sub-layer over the first passivation sub-layer, and 
 a thin nitrided layer sandwiched between the first and second passivation sub-layers, wherein the thin nitrided layer is separate and distinct from the second passivation sub-layer. 
   
     
     
         11 . The device of  claim 10  comprising an intermediate dielectric layer separating the substrate and the top dielectric layer, the intermediate dielectric layer includes a top metal level of the device, wherein the top metal level includes top level conductive lines which are in communication with the patterned top conductive layer. 
     
     
         12 . The device of  claim 11  wherein the patterned top conductive layer comprises a void above the top via and serves as an external contact of the semiconductor device for coupling to an external substrate. 
     
     
         13 . The device of  claim 12  wherein the top via openings are spaced about 2-3 μm apart and include sides of about 2-3 μm in length. 
     
     
         14 . The device of  claim 10  wherein the thin nitrided layer is disposed completely within a top surface portion of the first passivation sub-layer and directly contacts a bottom of the second passivation sub-layer. 
     
     
         15 . The device of  claim 14  wherein the thin nitrided layer comprises a composition which is different than a remaining portion of the first passivation sub-layer below the top surface portion. 
     
     
         16 . The device of  claim 15  wherein the thin nitrided layer includes a different composition than the second passivation sub-layer. 
     
     
         17 . The device of  claim 16  wherein the first passivation sub-layer comprises silicon oxide, doped silicon oxide or doped silicon nitride and the second passivation sub-layer comprises silicon nitride. 
     
     
         18 . The device of  claim 16  wherein the thin nitrided layer comprises silicon nitride or silicon oxynitride. 
     
     
         19 . The device of  claim 14  wherein the thickness of the first passivation sub-layer is about 6,000-14,000 Å and the thickness of the second passivation sub-layer is about 4,000-10,000 Å. 
     
     
         20 . The device of  claim 10  wherein the thin nitrided layer comprises a composition which is different than the first and second passivation sub-layers to improve the integrity of the passivation stack.