Packaged semiconductor device having attached chips overhanging the assembly pad

Abstract

A semiconductor device ( 200 ) comprising a semiconductor chip ( 201 ) has an electrically active side ( 201 a ) and an opposite electrically inactive side ( 201 b ); the active side bordered by an edge having a first length ( 202 a ), and the inactive side bordered by a parallel edge having a second length ( 202 b ) smaller than the first length; a substrate has an assembly pad ( 210 ) bordered by a linear edge having a third length ( 210 a ) equal to or smaller than the first length; the inactive chip side attached to the pad so that the edge of the first length is parallel to the edge of the third length; the active side of the attached chip forms an overhang over the pad, when the third length is smaller than the first length.

1 . A semiconductor device comprising:
 a semiconductor chip having an electrically active side and an opposite electrically inactive side, the active side bordered by an edge having a first length, the inactive side bordered by a parallel edge having a second length smaller than the first length;   a substrate having an assembly pad bordered by a linear edge having a third length smaller than the first length; and   the electrically inactive side attached to the pad, wherein the electrically active side of the attached chip forms an overhang over pad.   
     
     
         2 . (canceled) 
     
     
         3 . The device of  claim 1  wherein the overhang is along one edge of the attached chip. 
     
     
         4 . The device of  claim 1  wherein the overhang is along all four edges of the attached chip. 
     
     
         5 . The device of  claim 1  further including terminals surrounding the assembly pad, wherein the attached chip is connected to respective terminals by bonding wires. 
     
     
         6 . The device of  claim 5  wherein the assembly pad and the terminals are parts of a metal leadframe. 
     
     
         7 . The device of  claim 5  wherein the assembly pad and the terminals are metal layers and are integral to a laminated substrate. 
     
     
         8 . The device of  claim 5  further including a package encapsulating the chip, the bonding wires, and at least portions of the assembly pad and terminals. 
     
     
         9 . A semiconductor device comprising:
 a first semiconductor chip having an electrically active side and an opposite electrically inactive side, the active side bordered by an edge having a first length, the inactive side bordered by a parallel edge having a second length smaller than the first length;   a second semiconductor chip having an electrically active side and an opposite electrically inactive side, the active side bordered by an edge having a third length equal to, smaller than, or greater than the first length, the inactive side bordered by a parallel edge having a fourth length smaller than the third length;   the inactive chip side of the first chip attached to the active side of the second chip so that the edge of the first length is parallel to the edge of the third length;   an assembly pad having a top side bordered by an edge with a fifth length equal to or smaller than the third length; and   the inactive chip side of the second chip attached to the top pad side so that the edge of the third length is parallel to the edge of the fifth length, wherein the chips are assembled as a stack on the pad.   
     
     
         10 . The device of  claim 9  wherein the third length is equal to or smaller than the first length and the active side of the attached first chip forms an overhang over the active side of the second chip. 
     
     
         11 . The device of  claim 9  wherein the fifth length is smaller than the third length and the active side of the attached second chip forms an overhang over the top pad side. 
     
     
         12 . The device of  claim 9  further including terminals surrounding the assembly pad, wherein the attached chips are connected to respective terminals by bonding wires. 
     
     
         13 . The device of  claim 12  wherein the assembly pad and the terminals are parts of a metal leadframe. 
     
     
         14 . The device of  claim 12  wherein the assembly pad and the terminals are metal layers and are integral to a laminated substrate. 
     
     
         15 . The device of  claim 12  further including a package encapsulating the chips, the bonding wires, and at least portions of the assembly pad and terminals. 
     
     
         16 . A method for fabricating a semiconductor chip comprising:
 providing a semiconductor wafer of a first thickness having an electrically active side and an opposite electrically inactive side, the wafer including a plurality of device chips having linear borders between adjacent chips;   backgrinding the inactive wafer side to reduce the first wafer thickness to a smaller second thickness;   forming on the inactive wafer side a grid of linear grooves arrayed in parallel rows intersecting with parallel columns, the rows and columns at right angle to each other, the grooves having edges spaced by a first width and a depth smaller than the second thickness; and   forming on the active wafer side a matching grid of linear slits arrayed in parallel rows intersecting with parallel columns, the slits having edges spaced by a second width smaller than the first width and a depth merging with respective grooves, wherein merged slits and grooves form cuts singulating discrete rectangular chips from the wafer.   
     
     
         17 . The method of  claim 16 , wherein each singulated chip has an electrically active side bordered by an edge having a first length, and an opposite electrically inactive side bordered by a parallel edge having a second length smaller than the first length. 
     
     
         18 . The method of  claim 17  wherein the active side forms an overhang over the inactive side. 
     
     
         19 . The method of  claim 16  wherein the technique to form the grooves is selected from a group including laser saw, mechanical saw with wide blade, chemical etchant, and liquid jet. 
     
     
         20 . The method of  claim 16  wherein the technique to form the slits is a mechanical saw with thin blade. 
     
     
         21 . A method for fabricating a semiconductor device comprising:
 providing a semiconductor chip having an electrically active side and an opposite electrically inactive side, the active side bordered by an edge having a first length, the inactive side bordered by a parallel edge having a second length smaller than the first length;   providing a substrate having an assembly pad bordered by a linear edge having a third length smaller than the first length; and   attaching the inactive chip side to the pad.   
     
     
         22 . The method of  claim 21  wherein the substrate further includes terminals surrounding the assembly pad. 
     
     
         23 . The method of  claim 22  further including the processes of:
 connecting the chip to respective substrate terminals by bonding wires; and 
 encapsulating the chip and bonding wires in a packaging compound. 
 
     
     
         24 . A method for fabricating a semiconductor device comprising:
 providing a first semiconductor chip having an electrically active side and an opposite electrically inactive side, the active side bordered by an edge having a first length, the inactive side bordered by a parallel edge having a second length smaller than the first length;   providing a second semiconductor chip having an electrically active side and an opposite electrically inactive side, the active side bordered by an edge having a third length equal to, smaller, or greater than the first length, the inactive side bordered by a parallel edge having a fourth length smaller than the third length;   attaching the inactive chip side of the first chip to the active side of the second chip so that the edge of the first length is parallel to the edge of the third length;   providing a substrate having an assembly pad bordered by a linear edge with a fifth length equal to or smaller than the third length; and   attaching the inactive chip side of the second chip to the pad so that the edge of the third length is parallel to the edge of the fifth length.   
     
     
         25 . The method of  claim 24  wherein the third length is equal to or smaller than the first length and the active side of the attached first chip forms an overhang over the active side of the second chip. 
     
     
         26 . The method of  claim 24  wherein the fifth length is smaller than the third length and the active side of the attached second chip forms an overhang over the pad. 
     
     
         27 . The method of  claim 24  wherein the substrate further includes terminals surrounding the assembly pad. 
     
     
         28 . The method of  claim 27  further including the processes of:
 connecting the chips to respective substrate terminals by bonding wires; and 
 encapsulating the chips and bonding wires in a packaging compound.