Method for fabricating semiconductor device

Abstract

A method for fabricating a semiconductor device, including forming gate patterns over a substrate, forming conductive layer covering top and sidewalls of each gate pattern, forming a metal layer for a silicidation process over the conductive layer, and silicifying the conductive layer and the gate patterns using the metal layer.

What is claimed is: 
     
         1 . A method for fabricating a semiconductor device, comprising:
 forming gate patterns over a substrate;   forming conductive layer covering top and sidewalls of each gate pattern;   forming a metal layer for a silicidation process over the conductive layer; and   silicifying the conductive layer and the gate patterns using the metal layer,   wherein the forming of the conductive layer, covering top and sidewalls of each gate pattern, is performed by a sputtering process.   
     
     
         2 . The method of  claim 1 , wherein the sputtering process is performed by sequentially depositing a material layer for the conductive layer on top and each sidewall of an upper portion of each gate pattern. 
     
     
         3 . The method of  claim 1 , wherein the forming of the conductive layer covering top and sidewalls of each gate pattern, includes:
 depositing a material layer for the conductive layer over the substrate with the gate patterns formed therein; and   performing an etch-hack process onto the material layer for the conductive layer until a surface of a first interlayer dielectric layer between the gate patterns is exposed.   
     
     
         4 . The method of  claim 3 , wherein the material layer or the conductive layer is deposited by an Atomic Layer Deposition (ALD) process, a Chemical Vapor Deposition (CVD) process, or a sputtering process. 
     
     
         5 . The method of  claim 3 , further comprising:
 forming a second interlayer dielectric layer over the first interlayer dielectric layer and the conductive layer after performing the etch-back process;   performing a planarization process removing a portion of the second interlayer dielectric layer to expose a surface of the conductive layer; and   removing the second interlayer dielectric layer.   
     
     
         6 . A method for fabricating a semiconductor device, comprising:
 forming a first conductive layer and a first hard mask layer over a substrate;   forming a plurality of gate patterns by etching the first hard mask layer and the first conductive layer;   filling gap regions between the plurality of gate patterns with an insulation layer;   forming trenches by removing the first hard mask layer;   etching the insulation layer on internal sidewalls of the trenches by a predetermined thickness in order to increase a width of the trenches; and   filling the trenches having increased width with a second conductive layer.   
     
     
         7 . The method of  claim 6 , wherein the insulation layer is formed of a material having a high etch selectivity with respect to the first hard mask layer. 
     
     
         8 . The method of  claim 7 , wherein the first hard mask layer includes a nitride layer, and the nitride layer includes an oxide layer. 
     
     
         9 . The method of  claim 6 , further comprising:
 forming a second hard mask layer over the insulation layer, after the filling the gap regions between the plurality of gate patterns with the insulation layer.   
     
     
         10 . The method of  claim 6 , further comprising:
 recessing the insulation layer to a predetermined depth to form recesses; and   filling the recesses with a second hard mask layer.   
     
     
         11 . The method of  claim 10 , wherein the second hard mask layer is formed of a material having a high etch selectivity with respect to the insulation layer and the first hard mask layer. 
     
     
         12 . The method of  claim 10 , wherein the forming the trenches by removing the first hard mask layer,
 the first hard mask layer is removed by using the second hard mask layer as an etch barrier.   
     
     
         13 . The method of  claim 10 , wherein the etching the insulation layer on the internal sidewalls of the trenches by a predetermined thickness,
 the insulation layer exposed through the internal sidewalls of the trenches is etched by a predetermined thickness by using the second hard mask layer as an etch barrier.   
     
     
         14 . The method of  claim 10 , further comprising:
 removing the second hard mask layer, after etching the insulation layer on the internal sidewalls of the trenches by a predetermined thickness.   
     
     
         15 . The method of  claim 6 , further comprising:
 performing an etch-back process onto the insulation layer to expose sidewalls of the second conductive layer; and   silicifying the exposed second conductive layer.   
     
     
         16 . The method of  claim 6 , wherein the second conductive layer has a wider width than the first conductive layer.