Storage device, nonvolatile memory and method operating same
Abstract
A method of operating a storage device includes; counting a number of fast cycles for the memory block when a program interval between two successive program operations directed to memory cells of the memory block is less than a minimal program interval, and/or when an erase interval between two successive erase operations directed to the memory block is less than a minimal erase interval, and selecting the memory block to be erased by an erase operation or selecting memory cells of the memory block to be programmed by a program operation in response to the counted number of fast cycles for the memory block.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A method of operating a storage device including a memory controller and a nonvolatile memory including a memory block, the method comprising:
counting a number of fast cycles for the memory block when a program interval between two successive program operations directed to memory cells of the memory block is less than a minimal program interval, and/or when an erase interval between two successive erase operations directed to the memory block is less than a minimal erase interval; and selecting the memory block to be erased by an erase operation or selecting memory cells of the memory block to be programmed by a program operation in response to the counted number of fast cycles for the memory block.
2 . The method of claim 1 , wherein the counting of fast cycles for the memory block comprises:
executing a current erase operation directed to the memory block; determining the erase time interval between execution of the current erase operation and execution of a previous erase operation directed to the memory block; and comparing the erase time interval to a first threshold value.
3 . The method of claim 2 , wherein the counting of fast cycles for the memory block comprises:
resetting the number of fast cycles for the memory block when the erase time interval is greater than a second threshold value that is greater than the first threshold value.
4 . The method of claim 2 , wherein the counting of fast cycles for the memory block comprises:
decreasing the counted number of fast cycles for the memory block when the erase time interval is greater than a third threshold value that is greater than the first threshold value.
5 . The method of claim 2 , wherein the determining of the erase time interval comprises:
reading at least one time stamp for the selected memory block; and calculating the erase time interval between the current erase operation and the at least one time stamp.
6 . The method of claim 5 , further comprising:
updating the time stamp for the selected memory block with a time at which the current erase operation is completed.
7 . The method of claim 1 , wherein the counting of fast cycles for the memory block comprises:
performing a current programming operation directed to the memory block; detecting the program interval between a current program operation directed to memory cells of the memory block and a previous program operation directed to memory cells of the memory block; and increasing the counted number of fast cycles for the memory block when the program interval is less than the first threshold value.
8 . The method of claim 7 , wherein the detecting of the program interval comprises:
reading at least one time stamp for the memory block; and calculating a time interval between a time when the current program operation is completed and the at least one time stamp.
9 . The method of claim 8 , wherein the at least one time stamp indicates a time at which the current program operation is completed for a first word line of the memory block.
10 . The method of claim 8 , wherein the at least one time stamp indicates a time at which the current program operation is completed for a last word line of the memory block.
11 . The method of claim 8 , wherein the at least one time stamp indicates an average of total program operation times for memory cells connected to a plurality of word lines in the memory block by the current program operation.
12 . A method of operating a storage device including a memory controller and a nonvolatile memory including a plurality of memory blocks, the method comprising:
respectively counting a number of fast cycles for each one of the plurality of memory blocks when a program interval between two successive program operations directed to memory cells of each memory block is less than a minimal program interval, and/or when an erase interval between two successive erase operations directed to each of the memory blocks is less than a minimal erase interval; calculating a wear index for each one of the plurality of memory blocks based on the counted number of fast cycles for each one of the plurality of memory blocks, and a number of erase operations directed to each one of the plurality of memory blocks; and selecting a memory block from among the plurality of memory blocks to be erased by an erase operation or selecting memory cells of the memory block to be programmed by a program operation in response to the counted number of fast cycles for the selected memory block.
13 . The method of claim 12 , wherein the selecting of the memory block from among the plurality of memory is performed further in response to a wear index for the selected memory block.
14 . The method of claim 13 , further comprising:
reading first data from a first memory block having the highest wear index among the plurality of memory blocks; reading second data from a second memory block having the lowest wear index among the plurality of memory blocks; programming the first data to a third memory block; erasing the first memory block; and programming the second data to the erased first memory block.
15 . The method of claim 12 , wherein the selecting of the memory block from among the plurality of memory blocks comprises selecting the memory block having a lowest wear index for a plurality of spare memory blocks.
16 . A method of operating a nonvolatile memory device having a memory cell array divided into memory blocks, the method comprising:
counting a number of fast cycles for each one of the memory blocks when a program interval between two successive program operations directed to memory cells of each memory block is less than a minimal program interval, and/or when an erase interval between two successive erase operations directed to each memory block is less than a minimal erase interval; and selecting a memory block among the memory blocks to be erased by an erase operation or selecting memory cells of the memory block to be programmed by a program operation in response to the counted number of fast cycles for the memory block.
17 . The method of claim 16 , further comprising:
prohibiting the erase operation or the program operation when the selected memory block has a counted number of fast cycles greater than a prohibition threshold value.
18 . The method of claim 17 , further comprising:
releasing prohibition of the selected memory block for the erase operation or the program operation following a cure time interval.
19 . The method of claim 18 , further comprising:
programming dummy data to the selected memory block.
20 . The method of claim 18 , wherein the cure time interval is determined by referencing at least one time stamp associated with the selected memory block.Join the waitlist — get patent alerts
Track US2016180942A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.