Controlling memory access conflict of threads on multi-core processor with set of highest priority processor cores based on a threshold value of issued-instruction efficiency

Abstract

A multi-core processor system includes multiple cores and memory accessible from the cores, where a given core is configured to detect among the cores, first cores having a highest execution priority level; identify among the detected first cores, a second core that caused access conflict of the memory; and control a third core that is among the cores, excluding the first cores and the identified second core, the third core being controlled to execute for a given interval during an interval when the access conflict occurs, a thread that does not access the memory.

What is claimed is: 
     
         1 . A multi-core processor system comprising
 a plurality of cores; and   memory accessible from the cores, wherein a given core among the cores is configured to:   detect among the cores, first cores having a highest execution priority level,   identify based on issued-instruction efficiency calculated based on a cycle count and an issued instruction count of each of the cores, a second core that caused access conflict of the memory with the first cores, and   cause a third core other than the first cores and the second core, to execute for a given interval during an interval when the access conflict occurs, a thread that does not access the memory.   
     
     
         2 . The multi-core processor system according to  claim 1 , wherein the given interval is an interval split from the interval when the access conflict occurs, and split according to a thread allocated to the third core and a thread that does not access the memory. 
     
     
         3 . A control method of a multi-core processor system comprising a plurality of cores and memory accessible from the cores, the control method causing one of the cores to execute:
 detecting among the cores, first cores having a highest execution priority level;   detecting based on issued-instruction efficiency calculated based on a cycle count and an issued instruction count of each of the cores,   
       a second core that caused access conflict of the memory with the first cores; and
 causing a third core other than the first cores and the second core, to execute for a given interval during an interval when the access conflict occurs, a thread that does not access the memory. 
 
     
     
         4 . The control method according to  claim 3 , wherein the given interval is an interval split from the interval when the access conflict occurs, and split according to a thread allocated to the third core and a thread that does not access the memory.