Processor system and control method thereof

Abstract

A processor system according to the present invention includes a storage unit, a control information area that stores an access prohibit flag capable of switching from an allow side to a prohibit side, a main PEa that issues an access request to the storage unit and a request for rewriting a copy register, a security PE that evaluates whether or not the request for rewriting the copy register is valid, the copy register that stores, when the access prohibit flag is set to the allow side, a value corresponding to the allowance and, when the access prohibit flag is set to the prohibit side, a value corresponding to an evaluation result by the security PE, and an access control circuit that controls whether or not to allow access from the main PEa to the storage unit based on an output value from the copy register.

1 .- 8 . (canceled) 
     
     
         9 . A method for controlling a processor system comprising:
 a step of setting an access prohibit flag to be valid and setting a temporal access flag to be invalid, the access prohibit flag being a flag for prohibiting an access to a memory, the temporal access flag being stored in a register and being a flag for permitting a temporal access to the memory over an accessing period;   a step of, when an authentication information for the temporal access to the memory is determined to be valid, setting the temporal access flag to be valid;   a step of, when the temporal access flag is set to be valid, permitting the temporal access to the memory by setting the access prohibit flag to be invalid; and   a step of, when the processor system is reset, setting the access prohibit flag to be valid and setting the temporal access flag to be invalid.   
     
     
         10 . The control method of the processor system according to  claim 9 , wherein the memory is a non-volatile memory. 
     
     
         11 . The control method of the processor system according to  claim 10 , wherein the temporal access is at least one of a write access or an erase access to the non-volatile memory. 
     
     
         12 . The control method of the processor system according to  claim 9 , further comprising a step of comparing the authentication information for the temporal access to the memory with a predetermined authentication information stored in an authentication information storage unit, wherein
 in the step of setting the temporal access flag to be valid, when the authentication information for the temporal access to the memory is determined to be valid in a result of the comparison, the temporal access flag is set to be valid.   
     
     
         13 . The control method of the processor system according to  claim 11 , wherein the temporal access is issued from a processing element to the non-volatile memory. 
     
     
         14 . The control method of the processor system according to  claim 13 , wherein the processing element includes lock-step processors. 
     
     
         15 . The control method of the processor system according to  claim 9 , wherein the authentication information for the temporal access to the memory is determined to be valid by a security processor element. 
     
     
         16 . The control method of the processor system according to  claim 9 ,
 wherein the memory includes a first memory area and a second memory area,   wherein the temporal access flag includes a first temporal access flag corresponding to the first memory area and a second temporal access flag corresponding to the second memory area,   wherein when the authentication for the temporal access to the first memory area is valid, the first temporal access flag is set to permit the temporal access to the first memory area, and   wherein when the authentication for the temporal access to the second memory area is valid, the second temporal access flag is set to permit the temporal access to the second memory area.