Modified fin cut after epitaxial growth

Abstract

A method of forming a gate located above multiple fin regions of a semiconductor device. The method may include removing unwanted fin structures after epitaxially growing junctions.

1 . A semiconductor structure comprising:
 a first plurality of fins located in a first region of a substrate, wherein a first junction is located on a first set of fins in the first plurality of fins;   a second plurality of fins located in a second region of the substrate, wherein a second junction is located on a second set of fins in the second plurality of fins;   an intermediate plurality of fins located in an intermediate region of the substrate, wherein the intermediate region is located between the first region and the second region, wherein the length of the intermediate plurality of fins is substantially shorter than a length of the first plurality of fins; and   a gate running substantially perpendicular to the first plurality of fins, the intermediate plurality of fins, and the second plurality of fins.   
     
     
         2 . The structure of  claim 1 , wherein the first junction comprises a semiconductor material. 
     
     
         3 . The structure of  claim 2 , wherein the semiconductor material comprises silicon, silicon-germanium or silicon-carbon. 
     
     
         4 . The structure of  claim 1 , wherein the second junction material comprises a semiconductor material. 
     
     
         5 . The structure of  claim 4 , wherein the semiconductor material comprises silicon, silicon-germanium or silicon-carbon. 
     
     
         6 . The structure of  claim 1 , wherein the substrate is a semiconductor on insulator substrate. 
     
     
         7 . The structure of  claim 1 , wherein the fin pitch amongst the fins is substantially uniform. 
     
     
         8 . The structure of  claim 1 , wherein the intermediate plurality of fins is only located beneath the gate. 
     
     
         9 . The structure of  claim 1 , wherein the gate has a substantially uniform density. 
     
     
         10 . A semiconductor structure comprising:
 a first plurality of fins located in a first region of a substrate, wherein a first junction is located on a first set of fins in the first plurality of fins;   a second plurality of fins located in a second region of the substrate, wherein a second junction is located on a second set of fins in the second plurality of fins;   an intermediate plurality of fins located in an intermediate region of the substrate, wherein the intermediate region is located between the first region and the second region, wherein the length of the intermediate plurality of fins is substantially shorter than a length of the first plurality of fins; and   a gate running substantially perpendicular to the first plurality of fins, the intermediate plurality of fins, and the second plurality of fins,   wherein the fin pitch amongst the fins is substantially uniform, and   wherein the gate has a substantially uniform density.   
     
     
         11 . The structure of  claim 10 , wherein the first junction comprises a semiconductor material. 
     
     
         12 . The structure of  claim 11 , wherein the semiconductor material comprises silicon, silicon-germanium or silicon-carbon. 
     
     
         13 . The structure of  claim 10 , wherein the second junction material comprises a semiconductor material. 
     
     
         14 . The structure of  claim 13 , wherein the semiconductor material comprises silicon, silicon-germanium or silicon-carbon. 
     
     
         15 . The structure of  claim 10 , wherein the substrate is a semiconductor on insulator substrate.