US2016172308A1PendingUtilityA1

Overlay mark

Assignee: UNITED MICROELECTRONICS CORPPriority: Sep 26, 2014Filed: Feb 24, 2016Published: Jun 16, 2016
Est. expirySep 26, 2034(~8.2 yrs left)· nominal 20-yr term from priority
H10P 74/203H10P 74/23H10W 46/301H10W 20/4451H10W 46/00H01L 23/544H01L 23/53271H01L 2223/54426H01L 21/0332G03F 7/70633
46
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Claims

Abstract

An overlay mark applied to a LELE-type double patterning lithography (DPL) process including a first lithography step, a first etching step, a second lithography step and a second etching step in sequence is described. The overlay mark includes a first x-directional pattern and a first y-directional pattern of a previous layer, second x-directional and y-directional patterns of a current layer defined by the first lithography step, and third x-directional and y-directional patterns of the current layer defined by the second lithography step. The second x-directional patterns and the third x-directional patterns are arranged alternately beside the first x-directional pattern. The second y-directional patterns and the third y-directional patterns are arranged alternately beside the first y-directional pattern.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An overlay mark applied to a double patterning lithography (DPL) process including a first lithography step, a first etching step, a second lithography step and a second etching step in sequence, comprising:
 a first x-directional pattern and a first y-directional pattern of a previous layer;   a plurality of second x-directional patterns and a plurality of second y-directional patterns of a current layer, defined by the first lithography step; and   a plurality of third x-directional patterns and a plurality of third y-directional patterns of the current layer, defined by the second lithography step,   wherein the second x-directional patterns and the third x-directional patterns are arranged alternately beside the first x-directional pattern, and the second y-directional patterns and the third y-directional patterns are arranged alternately beside the first y-directional pattern.   
     
     
         2 . The overlay mark of  claim 1 , wherein among a first group including the first x-directional pattern and the first y-directional pattern, a second group including the second x-directional patterns and the second y-directional patterns, and a third group including the third x-directional patterns and the third y-directional patterns, each group independently has a trench form or a solid line form for each pattern in the group. 
     
     
         3 . The overlay mark of  claim 1 , wherein among a first group including the first x-directional pattern and the first y-directional pattern, a second group including the second x-directional patterns and the second y-directional patterns, and a third group including the third x-directional patterns and the third y-directional patterns, each group independently has a linear shape or a non-linear shape for each pattern in the group. 
     
     
         4 . The overlay mark of  claim 1 , wherein the previous layer comprises a conductive layer to be electrically connected with, and the current layer comprises an insulating layer covering the conductive layer. 
     
     
         5 . The overlay mark of  claim 4 , wherein the conductive layer comprises doped polysilicon. 
     
     
         6 . The overlay mark of  claim 4 , wherein the DPL process is for forming dense contact openings in the insulating layer. 
     
     
         7 . The overlay mark of  claim 4 , wherein the third x-directional patterns and the third y-directional patterns of the current layer defined by the second lithography step are all trench patterns in a photoresist layer. 
     
     
         8 . The overlay mark of  claim 4 , wherein the second x-directional patterns and the second y-directional patterns defined by the first lithography step are all formed in a hard mask layer. 
     
     
         9 . The overlay mark of  claim 8 , wherein the hard mask layer comprises an advanced patterning film (APF), silicon nitride (SiN), or titanium nitride (TiN).

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