US2016172307A1PendingUtilityA1

Method of manufacturing semiconductor device

Assignee: RENESAS ELECTRONICS CORPPriority: Jul 7, 2014Filed: Feb 15, 2016Published: Jun 16, 2016
Est. expiryJul 7, 2034(~8 yrs left)· nominal 20-yr term from priority
H10W 72/5522H10W 74/00H10W 70/656H10W 72/075H10W 72/073H10W 72/884H10W 72/5449H10W 90/754H10W 72/932H10W 46/607H10W 46/401H10W 46/101H10W 46/103H10W 46/106H10W 72/0198H10W 90/734H10P 72/0618H10P 72/0614H10P 54/00H10W 74/117H10W 72/5525H10W 46/407H10W 90/00H10W 74/016H10W 74/014H10W 70/041H10W 46/00H01L 21/78H01L 21/565H01L 21/4825H01L 2223/54446H01L 23/544
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Claims

Abstract

Reading reliability of a code formed in a semiconductor device is improved. A manufacturing method of semiconductor devices according to one embodiment includes a step of forming a sealing body MR in a plurality of device regions DVP with a code (first identification information) MK 3 being formed outside the device regions DVP of a wiring substrate. Also, the manufacturing method of semiconductor devices according to one embodiment includes a step of, after forming the sealing body MR, reading the code MK 3 and affixing another code (second identification information) to the sealing body MR. Further, before the step of forming the sealing body MR, a dam part DM is formed between a marking region MKR in which the code MK 3 is formed and the device regions DVP.

Claims

exact text as granted — not AI-modified
1 - 13 . (canceled) 
     
     
         14 . A method of manufacturing semiconductor devices, comprising the steps of:
 (a) providing a base material, the base material including:
 a first surface having a first side, and a second side opposite the first side, 
 a plurality of device regions located between the first side and the second side in plan view, 
 a first frame region located between the plurality of device regions and the first side in plan view, 
 a second frame region located between the plurality of device regions and the second side in plan view, 
 a marking region provided in the second frame region in plan view, 
 first identification information affixed to the marking region, and 
 a dam part provided in the second frame region in plan view, and located between the plurality of device regions and the marking region in plan view; 
   (b) after the step (a), mounting a plurality of semiconductor chips in the plurality of device regions, respectively, in plan view;   (c) after the step (b), clamping the base material with a first metal mold and a second metal mold such that the plurality of semiconductor chips are located inside a cavity provided in the first metal mold;   (d) after the step (c), forming a sealing body by supplying resin into the cavity from the first frame region of the base material; and   (e) after the step (d), cutting a part of each of the base material and the sealing body sealing the plurality of semiconductor chips.   
     
     
         15 . The method of manufacturing semiconductor devices according to  claim 14 ,
 wherein the first metal mold has a gate part in communication with the cavity and a vent part arranged on the opposite side of the gate part through the cavity and in communication with the cavity, and   wherein, in the step (b), the resin is supplied from the gate part arranged on the first frame region of the base material and a gas inside the cavity is discharged from the vent part arranged on the second frame region of the base material.   
     
     
         16 . The method of manufacturing semiconductor devices according to  claim 14 ,
 wherein the base material is a wiring substrate having a first insulating film formed on the first frame region,   wherein a plurality of gate patterns, which are metal patterns exposed from the first insulating film, are formed on the first frame region and are arranged at a position overlapping a supply port of the resin in the step (b),   wherein a plurality of vent patterns, which are trench patterns formed in the first insulating film, are formed on the second frame region and arranged at a position overlapping an outlet of a gas inside the cavity in the step (b), and   wherein a width, which is a length in an extending direction of the first side, of each of the plurality of gate patterns is greater than a width, which is a length in the extending direction of the first side, of each of the plurality of vent patterns.   
     
     
         17 . The method of manufacturing semiconductor devices according to  claim 16 ,
 wherein the plurality of vent patterns are formed in the second frame region, and   wherein the marking region is located between adjacent ones of the plurality of vent patterns.   
     
     
         18 . The method of manufacturing semiconductor devices according to  claim 14 ,
 wherein the base material has:
 an insulating layer, 
 a wiring formed on the insulating layer, and 
 an insulating film covering the wiring, and 
   wherein, in a cross-sectional view, the dam part comprises a trench having a bottom surface, which is a part of the insulating layer of the base material.   
     
     
         19 . The method of manufacturing semiconductor devices according to  claim 14 ,
 wherein the base material has:
 an insulating layer, 
 a wiring formed on the insulating layer, and 
 an insulating film covering the wiring, and 
   wherein, in a cross-sectional view, the dam part protrudes from a surface of the insulating film.

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