US2016172304A1PendingUtilityA1

Semiconductor device including air gaps and method of fabricating the same

Assignee: SK HYNIX INCPriority: Dec 26, 2012Filed: Feb 12, 2016Published: Jun 16, 2016
Est. expiryDec 26, 2032(~6.4 yrs left)· nominal 20-yr term from priority
H10W 20/036H10W 72/00H10W 20/076H10W 20/072H10W 20/069H10W 20/48H10W 20/46H10W 20/20H10W 10/021H10W 10/20H10W 10/17H10W 10/014H10W 20/425H10B 12/485H10B 12/482H10B 12/0335H01L 23/53266H01L 27/10855H01L 23/535H01L 23/5329
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Claims

Abstract

This technology provides a semiconductor device and a method of fabricating the same, which may reduce parasitic capacitance between adjacent conductive structures, The method of fabricating a semiconductor device may include forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming sacrificial spacers over sidewalis of the contact holes, forming first plugs recessed into the respective contact holes, forming air gaps by removing the sacrificial spacers, forming capping structures capping the air gaps while exposing top surfaces of the first plugs, and forming second plugs over the first plugs.

Claims

exact text as granted — not AI-modified
1 - 14 . (canceled) 
     
     
         15 . A semiconductor device comprising:
 a plurality of bit line structures formed over a substrate;   storage node contact holes formed to have sidewalls of the bit line structures exposed therethrough;   silicon plugs recessed and formed in the respective storage node contact holes;   air gaps formed between the sidewalls of the bit line structures and the silicon plugs;   capping layer patterns formed over the air gaps;   passivation layers formed over the respective capping layer patterns; and   metal plugs formed over the respective silicon plugs,   wherein the air gaps are capped with the respective capping layer patterns and passivation layers.   
     
     
         16 . The semiconductor device of  claim 15 , wherein the capping layer patterns comprise oxide of the silicon plugs. 
     
     
         17 . The semiconductor device of  claim 15 , wherein the passivation layers are formed of a spacer type, which covers upper sides and sidewalls of the storage node contact holes. 
     
     
         18 . The semiconductor device of  claim 15 , wherein the passivation layers comprise silicon nitride. 
     
     
         19 . The semiconductor device of  claim 15 , wherein:
 each silicon plug comprises a polysilicon layer, and   each metal plug comprises a tungsten layer.   
     
     
         20 . The semiconductor device of  claim 15 , further comprising:
 metal silicide formed between the silicon plugs and the metal plugs.

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