Power management in a discrete memory portion

Abstract

Systems and methods of operating a computing system may involve receiving, at a control interface, an instruction to alter a power state at a memory device, and directing, by the control interface, a controller to control a power supply to a memory device channel to alter the power state in the memory device.

We claim: 
     
         1 . An apparatus comprising:
 a management component to power down a memory device, remove a clock from the memory device, power down one or more other memory devices and remove a clock from the one or more other memory devices, wherein powering down the memory device is to be conducted independently of powering down the one or more other memory devices; and   one or more registers to store information indicating that the memory device is to be powered down.   
     
     
         2 . The apparatus of  claim 1 , wherein at least one of the one or more registers is to store an address associated with the memory device. 
     
     
         3 . The apparatus of  claim 1 , wherein the management component is to power up the memory device independently of powering up the one or more other memory devices. 
     
     
         4 . At least one computer readable storage medium comprising a set of instructions which, when executed by an apparatus, cause the apparatus to:
 power down a memory device;   remove a clock from the memory device;   power down one or more other memory devices; and   remove a clock from the one or more other memory devices, wherein powering down the memory device is to be conducted independently of powering down the one or more other memory devices, and wherein one or more registers are to store information indicating that the memory device is to be powered down.   
     
     
         5 . The at least one computer readable storage medium of  claim 4 , wherein at least one of the one or more registers is to store an address associated with the memory device. 
     
     
         6 . The at least one computer readable storage medium of  claim 4 , wherein the instructions, when executed, cause the apparatus to power up the memory device independently of powering up one or more other memory devices.