Frequency-locked loop circuit and semiconductor integrated circuit

Abstract

A frequency-locked loop circuit includes a digital control oscillator that generates a clock, and an FLL (frequency-locked loop) controller that generates a frequency control code to control an oscillation frequency of the clock. The FLL controller includes a frequency comparison unit that compares a frequency of a clock generated by the digital control oscillator with a frequency of a multiplied reference clock, and a delay code control unit that generates, based on a comparison result of the frequency comparison unit, the frequency control code so that the frequency of the clock generated by the digital control oscillator matches the frequency of the multiplied reference clock, the frequency comparison unit determines the frequency of the clock, and the delay code control unit generates the frequency control code according to a determination result of the frequency comparison unit, and outputs the frequency control code to the digital control oscillator.

1 . A frequency-locked loop circuit comprising:
 a digital control oscillator that generates a clock; and   an FLL (frequency-locked loop) controller that generates a frequency control code to control an oscillation frequency of the clock, wherein the FLL controller comprises:   a frequency comparison unit that compares a frequency of a clock generated by the digital control oscillator with a frequency of a multiplied reference clock; and   a delay code control unit that generates, based on a comparison result of the frequency comparison unit, the frequency control code so that the frequency of the clock generated by the digital control oscillator matches the frequency of the multiplied reference clock,   the frequency comparison unit determines the frequency of the clock, and   the delay code control unit generates the frequency control code according to a determination result of the frequency comparison unit, and outputs the frequency control code to the digital control oscillator,   wherein the digital control oscillator comprises:   a reference voltage generation circuit generating a first reference voltage of which temperature dependence is substantially cancelled;   a current generation circuit generating a control current of which temperature dependence is substantially cancelled; and   an oscillation circuit that receives the first reference voltage and the control current, and generates a clock,   wherein the oscillation circuit has a function of controlling a frequency of a clock generated by the oscillation circuit according to a value of a frequency of the generated clock.   
     
     
         2 . The frequency-locked loop circuit according to  claim 1 , wherein
 the reference voltage generation circuit also generates a second reference voltage, and   the current generation circuit that receives the second reference voltage and generates the control current.   
     
     
         3 . The frequency-locked loop circuit according to  claim 2 , wherein
 the reference voltage generation circuit generates the first and second reference voltage by using temperature trimming information generated based on a result of temperature trimming performed by the reference voltage generation circuit and the current generation circuit, and   the current generation circuit generates the control current by using the frequency control code, the control current having substantially no temperature dependence.   
     
     
         4 . The frequency-locked loop circuit according to  claim 1 , wherein
 the oscillation circuit comprises:
 an integrating circuit that receives the first reference voltage; 
 a voltage control oscillator that oscillates based on a control voltage output from the integrating circuit; and 
 a self-feedback loop for the integrating circuit to compare the first reference voltage with a comparison voltage generated based on a frequency of a clock generated by the voltage control oscillator, and 
 the oscillation circuit controls a value of the control voltage based on the frequency of the clock generated by the voltage control oscillator. 
   
     
     
         5 . The frequency-locked loop circuit according to  claim 1 , wherein the FLL controller outputs an initial code held in a memory circuit as the frequency control code, during a period between a time immediately after resetting and a time when a normal operation period is started. 
     
     
         6 . The frequency-locked loop circuit according to  claim 1 , wherein the frequency comparison unit determines the frequency of the clock by using first and second thresholds being set to different values according to a multiplication factor. 
     
     
         7 . The frequency-locked loop circuit according to  claim 6 , wherein the first and second thresholds are set in such a manner that a difference between the first and second thresholds increases as a multiplication factor increases. 
     
     
         8 . The frequency-locked loop circuit according to  claim 6 , wherein when the frequency comparison unit determines that the frequency of the clock is less than the first threshold or greater than the second threshold, the delay code control unit generates the frequency control code to adjust the frequency of the clock, and when the frequency comparison unit determines that the frequency of the clock is equal to or greater than the first threshold and equal to or less than the second threshold, the delay code control unit outputs the frequency control code to maintain the present frequency of the clock. 
     
     
         9 . A frequency-locked loop circuit comprising:
 a digital control oscillator that generates a clock; and   a controller that generates a frequency control code to control an oscillation frequency of the clock, the controller generates, based on a comparison result, the frequency control code so that the frequency of the clock generated by the digital control oscillator matches the frequency of the multiplied reference clock,   wherein the controller determines the frequency of the clock, and   wherein the controller generates the frequency control code according to a determination result, and outputs the frequency control code to the digital control oscillator.   
     
     
         10 . The frequency-locked loop circuit according to  claim 9 , wherein the digital control oscillator comprises:
 a reference voltage generation circuit generating a first reference voltage according to temperature information;   a current generation circuit generating a control current according to the temperature information; and   an oscillation circuit that receives the first reference voltage and the control current, and generates a clock,   wherein the oscillation circuit controls a frequency of a clock generated by the oscillation circuit according to a value of a frequency of the generated clock.   
     
     
         11 . The frequency-locked loop circuit according to  claim 9 , wherein the digital control oscillator generates a first reference voltage of which temperature dependence is substantially cancelled,
 wherein the digital control oscillator generates a control current of which temperature dependence is substantially cancelled,   wherein the digital control oscillator receives the first reference voltage and the control current, and generates a clock, and   wherein the digital control oscillator controls a frequency of a clock generated by the oscillation circuit according to a value of a frequency of the generated clock.   
     
     
         12 . The frequency-locked loop circuit according to  claim 11 , wherein
 the digital control oscillator generates the first reference voltage and a second reference voltage by using temperature trimming information generated based on a result of temperature trimming performed by the reference voltage generation circuit and the current generation circuit, and   the digital control oscillator generates the control current by using the frequency control code, the control current having substantially no temperature dependence.