Semiconductor integrated circuit and operating method thereof

Abstract

A semiconductor integrated circuit and its operating method are provided. The present circuit has first and second supply terminals capable of supplying first and second power supply voltages respectively, an input voltage selection circuit coupled to the first and second supply terminals, and first and second power supply switches. The input voltage selection circuit includes a power-on reset circuit, an input voltage detection circuit and a control circuit. When the supply of the first or second power supply voltage to one of both supply terminals is detected upon completion of a power on reset operation, one of both power supply switches and the other thereof are controlled to on and off respectively. When the supply of both power supply voltages to both supply terminals is detected, the one thereof and the other thereof are respectively controlled to on and off according to the preset order of precedence.

1 - 21 . (canceled) 
     
     
         22 . A semiconductor integrated circuit comprising:
 a first supply terminal capable of supplying a first power supply voltage;   a second supply terminal capable of supplying a second power supply voltage;   an input voltage selection circuit coupled to the first supply terminal and the second supply terminal;   a first power supply switch; and   a second power supply switch,   wherein the input voltage selection circuit includes a power-on reset circuit, an input voltage detection circuit and a control circuit,   wherein in response to the supply of the first power supply voltage to the first supply terminal and the supply of the second power supply voltage to the second supply terminal, the power-on reset circuit generates a power on reset signal,   wherein the input voltage detection circuit generates a first voltage detection output signal in response to the supply of the first power supply voltage to the first supply terminal and generates a second voltage detection output signal in response to the supply of the second power supply voltage to the second supply terminal,   wherein the control circuit controls the first power supply switch and the second power supply switch in response to the power on reset signal, the first voltage detection output signal and the second voltage detection output signal,   wherein the input voltage detection circuit detects the supply of the first power supply voltage to the first supply terminal and the supply of the second power supply voltage to the second supply terminal at a timing of a change in the level of the power on reset signal responsive to an end of a power on reset operation of the power-on reset circuit,   wherein in a case where, at the timing of the change in the level of the power on reset signal, the input voltage detection circuit detects the supply of the first power supply voltage to the first supply terminal and the supply of the second power supply voltage to the second supply terminal, the control circuit controls one of the first power supply switch and the second power supply switch and the other thereof to an on state and an off state respectively after the end of the power on reset operation,   wherein in said case, the one of the first power supply switch and the second power supply switch and the other thereof are respectively controlled to the on state and the off state in accordance with an order of precedence set to the control circuit in advance, and   wherein the one thereof controlled to the on state supplies the first power supply voltage or the second power supply voltage supplied to the first supply terminal or the second supply terminal to the load.   
     
     
         23 . The semiconductor integrated circuit according to  claim 22 , further comprising:
 a first external output terminal and a second external output terminal which supply the first power supply voltage or the second power supply voltage to a first external load and a second external load taken as the load respectively; and   an output P channel MOS transistor coupled between the first external output terminal and the second external output terminal,   wherein when either of the first power supply switch and the second power supply switch is controlled to an on state after the end of the power on reset operation, the output P channel MOS transistor is controlled to an on state by the control circuit, and   wherein the control of the output P channel MOS transistor to the on state enables the first power supply voltage or the second power supply voltage to be supplied to the second external load through the output P channel MOS transistor and the second external output terminal.   
     
     
         24 . The semiconductor integrated circuit according to  claim 23 , wherein the first external output terminal is configured to supply the first power supply voltage or the second power supply voltage to the first external load corresponding to another semiconductor integrated circuit taken as an active device, and
 wherein the output P channel MOS transistor and the second external output terminal are configured to supply the first power supply voltage or the second power supply voltage to the second external load taken as a battery.   
     
     
         25 . The semiconductor integrated circuit according to  claim 24 , wherein the input voltage selection circuit further comprises:
 an input voltage selection switch; and   a gate drive circuit,   wherein the input voltage selection switch includes a first input P channel MOS transistor and a second input P channel MOS transistor, the first input P channel MOS transistor having a source coupled to the first supply terminal and the second input P channel MOS transistor having a source coupled to the second supply terminal,   wherein during a power on reset period of the power-on reset circuit, the gate drive circuit controls both of the first and second input P channel MOS transistors of the input voltage selection switch to an on state, and   wherein during the power on reset period, an operating voltage to be supplied to the power-on reset circuit is generated from a drain of the first input P channel MOS transistor or a drain of the second input P channel MOS transistor.   
     
     
         26 . The semiconductor integrated circuit according to  claim 25 , wherein, in said case, the gate drive circuit controls one of the first and second input P channel MOS transistors of the input voltage selection switch and the other thereof to an on state and an off state respectively in accordance with the order of precedence set to the control circuit in advance. 
     
     
         27 . The semiconductor integrated circuit according to  claim 26 , wherein the input voltage selection circuit further comprises:
 a voltage comparison/selection circuit having a first input terminal, a second input terminal and an output terminal,   wherein the first input terminal of the voltage comparison/selection circuit is coupled to the drain of the first input P channel MOS transistor of the input voltage selection switch,   wherein the second input terminal of the voltage comparison/selection circuit is coupled to the drain of the second input P channel MOS transistor of the input voltage selection switch,   wherein the operating voltage supplied to the power-on reset circuit is generated from the output terminal of the voltage comparison/selection circuit, and   wherein the voltage comparison/selection circuit compares a voltage of the first input terminal and a voltage of the second input terminal to select a high voltage and thereby outputs the high voltage as the operating voltage supplied from the output terminal to the power-on reset circuit.   
     
     
         28 . The semiconductor integrated circuit according to  claim 24 , further comprising:
 a step-down DC-DC converter and a linear regulator coupled in parallel between the first supply terminal and the first power supply switch,   wherein the linear regulator operates as a series regulator which quickly operates immediately after power-on based on the supply of the first power supply voltage to the first supply terminal, and   wherein the step-down DC-DC converter operates as a switching regulator having power efficiency higher than the linear regulator.   
     
     
         29 . The semiconductor integrated circuit according to  claim 28 , wherein the first supply terminal is configured to supply a power supply voltage based on a wireless power delivery to the first supply terminal through a first Schottky diode and an AC-DC conversion power supply voltage of an AC power supply coupling interface thereto through a second Schottky diode, and
 wherein the second supply terminal is configured to supply a USB power supply voltage of a USB coupling interface to the second supply terminal.