Scalable and reliable non-volatile memory cell

Abstract

Devices and methods for forming a device are disclosed. The method includes providing a substrate and forming a memory cell pair on the substrate. Each of a memory cell of the memory cell pair includes at least one transistor having first and second gates formed between first and second terminals and a third gate disposed over the second terminal. The first gate serves as an access gate (AG), the second gate serves as a storage gate and the third gate serves as an erase gate (EG). The first cell terminal serves as a bitline terminal and the second cell terminal serves as a source line terminal. The source line terminal is a raised source line terminal and is elevated with respect to the bit line terminal and the source line terminal is common to the memory cell pair.

What is claimed is: 
     
         1 . A device comprising:
 a substrate prepared with a memory cell region; and   first and second memory cells of a memory cell pair in the memory cell region, wherein the memory cell pair comprises
 first and second storage gates (SGs) of the first and second memory cells, wherein a SG includes a primary gate dielectric layer, a floating gate (FG) electrode layer, a control gate (CG) dielectric layer and a CG electrode layer, 
 an elevated source line terminal between the SGs of the memory cell pair, wherein the elevated source line terminal comprises a top surface extending above a top surface of the substrate and below a top surface of the FG electrode layer, 
 an erase gate (EG) over the elevated source line, the erase gate is isolated from first sidewalls of the SGs and source line terminal, 
 first and second access gates (AGs) adjacent to the SGs, and 
 first and second bitline terminals adjacent to the first and second AGs. 
   
     
     
         2 . The device of  claim 1  wherein:
 the primary gate dielectric layer is disposed over the substrate; 
 the FG electrode layer is disposed over the primary gate dielectric layer; 
 the CG dielectric layer is disposed over the FG electrode layer; and 
 the CG electrode layer is disposed over the CG dielectric layer. 
 
     
     
         3 . The device of  claim 2  wherein the first and second memory cells comprise sidewall storage gate dielectric layers disposed on sidewalls of the SGs. 
     
     
         4 . The device of  claim 1  wherein the AG and the SG share a common channel which is disposed between first and second cell terminals. 
     
     
         5 . The device of  claim 4  wherein the first cell terminal is the bitline terminal adjacent to the AG and the second cell terminal is the elevated source line terminal adjacent to the SG. 
     
     
         6 . The device of  claim 4  wherein the first and second cell terminals are first and second doped regions which include first polarity type dopants. 
     
     
         7 . The device of  claim 6  wherein the first doped region is a bitline doped region and the second doped region is a source line doped region, wherein the source line doped region is an elevated source line doped region which comprises a surface semiconductor layer disposed on the surface of the substrate while a lower portion is part of the substrate. 
     
     
         8 . The device of  claim 1  wherein the AG is coupled to a wordline (WL), the CG electrode is coupled to a control gate line (CGL) and the EG is coupled to an erase gate line (EGL). 
     
     
         9 . The device of  claim 8  wherein the EG and the CGs comprise substantially planar top surfaces, wherein the EG and the CGs are separated by CG sidewall dielectric layers. 
     
     
         10 . The device of  claim 4  wherein the AG is a gate spacer disposed on a sidewall of the SG proximate to the first cell terminal. 
     
     
         11 . The device of  claim 1  wherein the EG is isolated from the elevated source line by an EG dielectric. 
     
     
         12 . The device of  claim 1  wherein the first SG and the first AG are disposed between first and second cell terminals, wherein
 the first AG is proximate to the first cell terminal and the first SG is proximate to the second cell terminal, and 
 the first cell terminal is a first AG terminal and the second cell terminal is a second storage terminal. 
 
     
     
         13 . The device of  claim 12  wherein the first SG and the first AG are separated by a second AG terminal. 
     
     
         14 . The device of  claim 13  wherein the first and second cell terminals are first and second doped regions which include first polarity type dopants, wherein the first doped region serves as a bitline doped region and the second doped region serves as source line doped region. 
     
     
         15 . The device of  claim 12  wherein the AG comprises an AG gate electrode and an AG gate dielectric disposed on the substrate. 
     
     
         16 . A device comprising:
 a substrate prepared with a memory cell region; and   first and second memory cells of a memory cell pair disposed in the memory cell region, wherein the memory cell pair comprises
 first and second storage gates (SGs) of the first and second memory cells, wherein a SG includes a primary gate dielectric layer disposed over the substrate, a floating gate (FG) electrode layer disposed over the primary gate dielectric layer, a control gate (CG) dielectric layer disposed over the FG electrode layer and a CG electrode layer disposed over the CG dielectric layer, 
 an elevated source line terminal between the SGs of the memory cell pair, 
 an erase gate (EG) over the elevated source line, the erase gate is isolated from first sidewalls of the SGs and source line terminal, 
 first and second access gates (AGs) adjacent to the SGs, and 
 first and second bitline terminals adjacent to the first and second AGs. 
   
     
     
         17 . The device of  claim 16  wherein the elevated source line terminal comprises a top surface extending above a top surface of the substrate and below a top of the FG electrode layer. 
     
     
         18 . The device of  claim 16  wherein the elevated source line terminal is a heavily doped first polarity type elevated source line terminal. 
     
     
         19 . The device of  claim 15  wherein the EG and the CGs include a substantially planar top surfaces, wherein the EG and the CGs are separated by CG sidewall dielectric layers. 
     
     
         20 . The device of  claim 15  wherein each of the first and second AGs comprise an AG gate electrode and an AG gate dielectric disposed on the substrate.