Semiconductor device having high frequency wiring and dummy metal layer at multilayer wiring structure

Abstract

A semiconductor device includes a semiconductor substrate, a plurality of wiring layers provided on the semiconductor substrate, a high frequency wiring provided at a first layer in the plurality of wiring layers, and a plurality of dummy metals provided in a second layer provided between the semiconductor substrate and the first layer having the high frequency wiring. The plurality of wiring layers at a top view includes a high frequency wiring vicinity region and an external region surrounding the high frequency wiring vicinity region, the high frequency wiring vicinity region including a first region enclosed by an outer edge of the high frequency wiring and a second region surrounding the first region. The plurality of dummy metals are disposed dispersedly in the high frequency wiring vicinity region and in the external region respectively.

1 - 16 . (canceled) 
     
     
         17 . A semiconductor device, comprising:
 a semiconductor substrate;   a plurality of wiring layers provided on the semiconductor substrate;   a coil-shaped high frequency wiring in a plan view provided at a layer in the plurality of wiring layers; and   a plurality of first dummy metals provided in the layer including the high frequency wiring and inside of the high frequency wiring in the plan view,   wherein a plurality of second dummy metals is provided in the layer including the high frequency wiring and outside of the high frequency wiring in the plan view,   wherein a plurality of third dummy metals is provided in a layer next below the layer including the high frequency wiring and outside of the high frequency wiring,   wherein the third dummy metals are provided inside of the high frequency wiring and are not overlapped with the high frequency wiring in the plan view,   wherein a plurality of fourth dummy metals is provided in a same layer including the third dummy metals,   wherein the fourth dummy metals are provided outside of the high frequency wiring in the plan view,   wherein a plurality of fifth dummy metals is provided in the same layer including the third dummy metals,   wherein the fifth dummy metals are provided outside of the high frequency wiring in the plan view,   wherein the fifth dummy metals are provided overlapped with the high frequency wiring in the plan view,   wherein a guarding is provided at the layer in the plurality of wiring layers,   wherein the guarding surrounds the high frequency wiring in the plan view,   wherein a plurality of sixth dummy metals is provided in the layer including the high frequency wiring,   wherein the sixth dummy metals are provided outside of the guarding in the plan view,   wherein the second dummy metals are provided inside of the guarding in the plan view, and   wherein a mean density of a plurality of the first dummy metals and a mean density of a plurality of the second dummy metals are lower than a mean density of a plurality of the first dummy metals.   
     
     
         18 . The semiconductor device according to  claim 17 , wherein the high frequency wiring includes an inductor. 
     
     
         19 . A semiconductor device, comprising:
 a semiconductor substrate;   a plurality of wiring layers provided on the semiconductor substrate;   a coil-shaped high frequency wiring in a plan view provided at a layer in the plurality of wiring layers; and   a plurality of first dummy metals provided in the layer including the high frequency wiring and a high frequency wiring vicinity region in the plan view,   wherein a plurality of second dummy metals is provided in the layer including the high frequency wiring and outside of the high frequency wiring vicinity region in the plan view,   wherein a plurality of third dummy metals is provided in a layer next below the layer including the high frequency wiring and outside of the high frequency wiring vicinity region,   wherein the third dummy metals are provided in the high frequency wiring vicinity region and are not overlapped with the high frequency wiring in the plan view,   wherein a plurality of fourth dummy metals is provided in a same layer including the third dummy metals,   wherein the fourth dummy metals are provided outside of the high frequency wiring vicinity region in the plan view,   wherein a plurality of fifth dummy metals are provided in the same layer including the third dummy metals,   wherein the fifth dummy metals are provided outside of the high frequency wiring in the plan view,   wherein the fifth dummy metals are provided overlapped with the high frequency wiring in the plan view,   wherein a guarding is provided at the layer in the plurality of wiring layers,   wherein the guarding surrounds the high frequency wiring in the plan view,   wherein a plurality of sixth dummy metals is provided in the layer including the high frequency wiring,   wherein the sixth dummy metals are provided outside of the guarding in the plan view,   wherein the second dummy metals are provided inside of the guarding in the plan view, and   wherein a mean density of a plurality of the first dummy metals and a mean density of a plurality of the second dummy metals are lower than a mean density of a plurality of the first dummy metals.   
     
     
         20 . The semiconductor device according to  claim 19 , wherein the high frequency wiring includes an inductor. 
     
     
         21 . A semiconductor device, comprising:
 a semiconductor substrate;   a plurality of wiring layers provided on the semiconductor substrate;   a coil-shaped high frequency wiring in a plan view provided at a layer in the plurality of wiring layers; and   a plurality of first dummy metals provided in the layer including the high frequency wiring and inside of the high frequency wiring in the plan view,   wherein a plurality of second dummy metals is provided in the layer including the high frequency wiring and outside of the high frequency wiring in the plan view,   wherein a plurality of third dummy metals is provided in a layer below the layer including the high frequency wiring and outside of the high frequency wiring,   wherein the third dummy metals are provided inside of the high frequency wiring and are not overlapped with the high frequency wiring in the plan view,   wherein a plurality of fourth dummy metals is provided in a same layer including the third dummy metals,   wherein the fourth dummy metals are provided outside of the high frequency wiring in the plan view,   wherein a plurality of fifth dummy metals is provided in the same layer including the third dummy metals,   wherein the fifth dummy metals are provided outside of the high frequency wiring in the plan view,   wherein the fifth dummy metals are provided overlapped with the high frequency wiring in the plan view,   wherein a guard ring is provided at the layer in the plurality of wiring layers,   wherein the guard ring surrounds the high frequency wiring in the plan view,   wherein a plurality of sixth dummy metals is provided in the layer including the high frequency wiring,   wherein the sixth dummy metals are provided outside of the guard ring in the plan view, and   wherein the second dummy metals are provided inside of the guard ring in the plan view.   
     
     
         22 . The semiconductor device according to  claim 21 , wherein the high frequency wiring includes an inductor. 
     
     
         23 . The semiconductor device according to  claim 21 , wherein a mean density of a plurality of the first dummy metals and a mean density of a plurality of the second dummy metals are different than a mean density of a plurality of the first dummy metals.