Parallel arithmetic device, data processing system with parallel arithmetic device, and data processing program

Abstract

A parallel arithmetic device including a plurality of data wirings disposed in a first direction and a second direction; a plurality of flag wirings corresponding to the data wirings; a plurality of wiring coupling switches disposed each being disposed at respective intersections of the data wirings; and a plurality of processor elements surrounded by the data wirings. A processor element from among the plurality of the processor elements is configured to: perform an arithmetic process on data supplied from a first processor element based on a first flag supplied from the first processor element, the data being supplied on data wiring and the first flag being supplied on flag wiring; output a computation result to a second processor element on data wiring; and output a second flag based on the computation result to the second processor on flag wiring.

What is claimed is: 
     
         1 . A parallel arithmetic device comprising:
 a plurality of data wirings disposed in a first direction and a second direction;   a plurality of flag wirings corresponding to the data wirings;   a plurality of wiring coupling switches disposed each being disposed at respective intersections of the data wirings; and   a plurality of processor elements surrounded by the data wirings;   wherein a processor element from among the plurality of the processor elements is configured to:
 perform an arithmetic process on data supplied from a first processor element based on a first flag supplied from the first processor element, the data being supplied on data wiring and the first flag being supplied on flag wiring; 
 output a computation result to a second processor element on data wiring; and 
 output a second flag based on the computation result to the second processor on flag wiring. 
   
     
     
         2 . The parallel arithmetic device according to  claim 1 ,
 wherein each of the plurality of the processor elements comprises a instruction memory configured to store a plurality of operation instructions;   wherein each of the plurality of the processor elements is configured to perform an operation based on a selected operation instruction among the plurality of operation instructions.   
     
     
         3 . The parallel arithmetic device according to  claim 2 ,
 wherein each of plurality of wiring coupling switches is configured to control data wiring and vertical wiring disposed in the first direction based on an operation instruction read from an instruction memory, and to couple the processor elements using data wiring.   
     
     
         4 . The parallel arithmetic device according to  claim 2 ,
 wherein each of plurality of the processor elements comprises a plurality of arithmetic units each configured to perform an arithmetic process based on operation instructions stored in that processor element;   wherein each arithmetic element is configured to perform an arithmetic process on input data in accordance with an operation instruction read out from the instruction memory of that processor element.   
     
     
         5 . The parallel arithmetic device according to  claim 2 ,
 wherein each of plurality of the processor elements comprises a plurality of arithmetic units configured to perform an arithmetic process based on operation instructions stored in the processor element;   wherein each arithmetic element is configured to perform an arithmetic process in parallel on each of a plurality of sets of input data in accordance with one operation instruction read out from the instruction memory of that processor element.   
     
     
         6 . A parallel arithmetic device comprising:
 data wiring and flag wiring;   wiring coupling switches disposed as respective intersections of the data wiring;   a first processor element configured to output first data and a first flag;   a second processor element configured to receive the first data supplied on data wiring connecting the first processor element to the second processor element, to receive the first flag supplied on flag wiring connecting the first processor element and the second processor element, to perform an arithmetic process on the first data based on the first flag, and to output a computation result and a second flag corresponding to the computation result; and   a third processor element configured to receive the computation result supplied on data wiring connecting the second processor element to the third processor element, and to receive the second flag supplied on flag wiring connecting the second processor element to the third processor element.   
     
     
         7 . The parallel arithmetic device according to  claim 6 , wherein the second processor element includes a first arithmetic unit configured to perform a first arithmetic process on the first data, and a second arithmetic unit configured to perform a second arithmetic process on the first data in parallel with the first arithmetic process. 
     
     
         8 . The parallel arithmetic device according to  claim 7 , wherein the first arithmetic process is different from the second arithmetic process. 
     
     
         9 . The parallel arithmetic device according to  claim 8 , wherein the second processor element further includes an instruction memory configured to store operation instructions, the first arithmetic unit and the second arithmetic unit being configured according to the operation instructions stored on the instruction memory. 
     
     
         10 . The parallel arithmetic device according to  claim 6 , wherein the second processor element is configured to perform at least two arithmetic processes in parallel upon receipt of one operation instruction. 
     
     
         11 . A data processing system comprising:
 a data processing device comprising:
 a behavioral synthesis section configured to generates a structural description by unrolling, for behavioral synthesis purposes, a loop description that is included in an operation description and with no data dependency between iterations; and 
 a layout section configured to subject the structural description to logic synthesis and performs a place and route; and 
   a parallel arithmetic device comprising:
 data wiring and flag wiring; 
 wiring coupling switches disposed as respective intersections of the data wiring; 
 a first processor element configured to output first data and a first flag; 
 a second processor element configured to receive the first data supplied on data wiring connecting the first processor element to the second processor element, to receive the first flag supplied on flag wiring connecting the first processor element and the second processor element, to perform an arithmetic process on the first data based on the first flag, and to output a computation result and a second flag corresponding to the computation result; and 
 a third processor element configured to receive the computation result supplied on data wiring connecting the second processor element to the third processor element, and to receive the second flag supplied on flag wiring connecting the second processor element to the third processor element, 
   wherein the second processor element is dynamically configurable according to a state output by the data processing device.   
     
     
         12 . The data processing system according to  claim 11 , wherein the second processor element is dynamically configured as a circuit corresponding to an unrolled part of the loop description by using arithmetic units included in the second processor element. 
     
     
         13 . The data processing system according to  claim 11 , wherein the behavioral synthesis section divides the loop description with no data dependency between iterations into:
 a first loop description having a number of iterations according to a number of arithmetic units included in each of the first processor element, second processor element, and third processor element; and   a second loop description adapted to perform a loop process on the first loop description, and unrolls the first loop description.   
     
     
         14 . The data processing system according to  claim 11 , wherein the behavioral synthesis section performs behavioral synthesis by unrolling an outer loop of a multiple loop having an inner loop as well as the outer loop. 
     
     
         15 . The data processing system according to  claim 11 , wherein the behavioral synthesis section replaces the unrolled part of the loop description with a vector variable and outputs the vector variable as the structural description.