Meta plane operations for a storage device

Abstract

A method of operating a data storage device having a memory includes scheduling a first operation to be performed at one or more memory dies of a first meta plane of a plurality of meta planes of the memory. The first operation is to be performed during a particular time period. The method also includes determining that performance of the first operation consumes less than a threshold amount of power. The method further includes scheduling a second operation to be performed at one or more memory dies of a second meta plane of the plurality of meta planes, or at one of the dies in the same meta plane, during the particular time period and performing the first operation concurrently with the second operation. A peak amount of power corresponding to concurrent execution of the first operation and the second operation is less than the threshold amount of power.

What is claimed is: 
     
         1 . A method comprising:
 at a data storage device including a memory, the memory including a plurality of meta planes, each meta plane including a plurality of memory dies, performing:
 scheduling a first operation to be performed at one or more memory dies of a first meta plane of the plurality of meta planes, the first operation to be performed during a particular time period; 
 determining that performance of the first operation consumes less than a threshold amount of power; 
 scheduling a second operation to be performed at one or more memory dies of a second meta plane of the plurality of meta planes during the particular time period; and 
 performing the first operation concurrently with the second operation, wherein a peak amount of power corresponding to concurrent execution of the first operation and the second operation is less than the threshold amount of power. 
   
     
     
         2 . The method of  claim 1 , wherein the threshold amount of power corresponds to a peak power constraint associated with the memory. 
     
     
         3 . The method of  claim 1 , wherein:
 the first meta plane includes a first number of memory dies;   the second meta plane includes a second number of memory dies; and   the threshold amount of power corresponds to a particular peak amount of power of multiple operations that are concurrently performed at the plurality of meta planes.   
     
     
         4 . The method of  claim 1 , wherein the first operation comprises folding single-level cell (SLC) data stored at the first meta plane into multi-level cell (MLC) data. 
     
     
         5 . The method of  claim 4 , wherein the second operation comprises a SLC write operation. 
     
     
         6 . The method of  claim 5 , wherein the SLC write operation is performed at the second meta plane one memory die at a time. 
     
     
         7 . The method of  claim 5 , wherein the SLC write operation is based on data received from a host device coupled to the data storage device. 
     
     
         8 . The method of  claim 4 , wherein the second operation comprises an enhanced post-write read (EPWR) operation. 
     
     
         9 . The method of  claim 8 , further comprising performing, prior to the particular time period, a folding operation to write MLC data at the second meta plane, wherein the EPWR operation is performed to verify accuracy of the MLC data written at the second meta plane. 
     
     
         10 . The method of  claim 1 , wherein the first operation comprises a single-level cell (SLC) write operation, and wherein the second operation comprises an erase operation. 
     
     
         11 . The method of  claim 10 , wherein the erase operation is performed at the second meta plane one memory die at a time. 
     
     
         12 . The method of  claim 1 , wherein the first operation comprises a multi-level cell (MLC) direct write operation. 
     
     
         13 . The method of  claim 12 , wherein performing the MLC direct write operation includes performing interleaved lower page programming across the memory dies of the first meta plane and performing interleaved upper page programming across the memory dies of the first meta plane. 
     
     
         14 . The method of  claim 1 , wherein the first operation comprises an erase operation, and wherein the second operation comprises a compaction operation. 
     
     
         15 . The method of  claim 14 , further comprising:
 accessing stored parameter data to identify a first duration of the erase operation and to identify a second duration of compaction of a page of the memory during the compaction operation; and   determining a number of pages on which to perform the compaction operation based on the first duration divided by the second duration.   
     
     
         16 . The method of  claim 1 , wherein the first operation comprises an erase operation, and wherein the second operation comprises an enhanced post-write read (EPWR) operation. 
     
     
         17 . The method of  claim 16 , further comprising:
 accessing stored parameter data to identify a first duration of the erase operation and to identify a third duration of verification of a page of the memory during the EPWR operation; and   determining a number of pages on which to perform the EPWR operation based on the first duration divided by the second duration.   
     
     
         18 . A data storage device comprising:
 a memory including multiple dies, wherein a first set of dies of the multiple dies are grouped as a first meta plane and a second set of dies of the multiple dies are grouped as a second meta plane; and   a controller coupled to the memory, wherein the controller is configured to determine a first set of operations to be performed at the first set of dies during a particular time period and to determine one or more idle time periods associated with the second set of dies during the particular time period, wherein the controller is further configured to schedule a second operation to be performed at a second die of the second set of dies during at least one of the one or more idle time periods, and wherein a peak power consumption corresponding to multiple operations concurrently performed at the multiple memory dies during the particular time period is less than a threshold.   
     
     
         19 . The data storage device of  claim 18 , wherein the memory is configured to store first duration data corresponding to a first amount of time to complete execution of the first set of operations and second duration data corresponding to a first amount of time to complete execution of the second operation, and wherein the controller is configured to track an operation type identifier and an operation start time for each operation performed at each of the multiple dies. 
     
     
         20 . The data storage device of  claim 18 , wherein the second operation is a garbage collection operation, an erase operation, an enhanced post-write read (EPWR) operation, a folding operation, a multi-level cell (MLC) write, a single-level cell (SLC) write operation, or a combination thereof. 
     
     
         21 . The data storage device of  claim 18 , wherein the memory includes firmware, and wherein, responsive to a power-up event, the firmware is loaded from the memory to the controller and the controller is configured to initiate a set of erase operations to erase a set of blocks of the first set of dies, and wherein the first set of operations are configured to write data to the set of blocks. 
     
     
         22 . A method comprising:
 at a data storage device including a memory, the memory includes a meta plane that includes a plurality of memory dies, performing:
 determining a schedule of one or more first operations to be performed at one or more memory dies of the plurality of memory dies; 
 identifying a time period of the schedule during which a particular memory die of the plurality of memory dies is idle; and 
 updating the schedule to include a second operation to be performed at the particular memory die during the time period. 
   
     
     
         23 . The method of  claim 22  further comprising performing the one or more first operations and the second operation according to the updated schedule, wherein the one or more first operations include a folding operation, and wherein the second operation includes an enhanced post-write read (EPWR) operation. 
     
     
         24 . The method of  claim 23 , wherein the one or more first operations further include a single-level cell (SLC) write operation, and wherein the EPWR operation is selected for scheduling based on a rate being less than or equal to a threshold rate, wherein the rate is associated with a transfer of data from a host device to the data storage device. 
     
     
         25 . A data storage device comprising:
 a memory including a first set of dies associated with a first meta plane and a second set of dies associated with a second meta plane; and   a controller coupled to the memory, wherein the controller is configured to determine an incoming data rate of data received from a host device and to initiate a first set of operations at the first set of dies, wherein, in response to a determination that the incoming data rate is less than or equal to a threshold rate, the controller is configured to determine an idle time period of a first die of the first set of dies during an execution period of the first set of operations and to initiate a particular operation at the first die during the idle time period.   
     
     
         26 . The data storage device of  claim 25 , further comprising a buffer random-access memory configured to store the data received from the host device, wherein the controller is configured to calculate a duration of the execution period based on the incoming data rate, a first amount of time to transfer the received data from the buffer random-access memory to the memory, a second amount of time to write the data into the memory, or a combination thereof. 
     
     
         27 . The data storage device of  claim 25 , wherein the first set of operations includes a set of single-level cell (SLC) write operations, and wherein the particular operation includes a multi-level cell (MLC) write operation. 
     
     
         28 . The data storage device of  claim 25 , wherein the first set of operations includes a set of multi-level cell (MLC) write operations, and wherein the particular operation includes an enhanced post-write read (EPWR) operation, a garbage collection operation, an erase operation, a folding operation, or other background operation. 
     
     
         29 . The data storage device of  claim 25 , wherein the first set of operations includes a set of multi-level cell (MLC) direct write operations to write the incoming data at the first set of dies. 
     
     
         30 . The data storage device of  claim 25 , wherein the memory includes a three-dimensional (3D) memory configuration that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate, and wherein the memory includes circuitry associated with operation of the memory cells.