Mimcap structure in a semiconductor device package

Abstract

The disclosed technology relates generally to a semiconductor device package comprising a metal-insulator-metal capacitor (MIMCAP). In one aspect, the MIMCAP comprises portions of a first and second metallization layers in a stack of metallization layers, e.g., copper metallization layers formed by single damascene processes. The MIMCAP comprises a bottom plate formed in the first metallization layer, a first conductive layer on and in electrical contact with the bottom plate, a dielectric layer on and in contact with the first conductive layer, a second conductive layer on and in contact with the dielectric layer, and a top plate formed in the second metallization layer, on and in electrical contact with the second metal plate. The electrical contacts to the bottom and top plates of the MIMCAP formed in the first and second metallization layer are thereby established without forming separate vias between the plates and the metallization layers. In addition, the first conductive layer of the MIMCAP may extend beyond the surface of the dielectric and the second layer for forming other structures.

What is claimed is: 
     
         1 . A semiconductor device package comprising an interposer substrate configured to electrically connect to one or more semiconductor devices, the interposer substrate comprising:
 a metallization stack comprising a plurality of interconnected metallization layers including a lower layer and an upper layer that are vertically adjacent metallization layers within the metallization stack, at least portions of the upper and lower layers forming parts of a metal-insulator-metal capacitor (MIMCAP), wherein the MIMCAP comprises:
 a bottom plate which forms a part of the lower metallization layer, 
 a first conductive layer, at least a portion of which is formed on and in contact with the bottom plate, 
 a dielectric layer on and in contact with the first conductive layer, 
 a second conductive layer on and in contact with the dielectric layer, and 
 a top plate which forms a part of the upper metallization layer, the top plate being on and in contact with the second conductive layer, 
 wherein the first conductive layer laterally extends beyond areas of coverage covered by the dielectric layer and the second conductive layer. 
   
     
     
         2 . The semiconductor device package of  claim 1 , wherein the first conductive layer is further patterned in an area outside of an area covered by the MIMCAP. 
     
     
         3 . The semiconductor device package of  claim 2 , wherein the first conductive layer is patterned to form one or more patterned portions, wherein the patterned portions serve as contact portions for electrical circuit elements. 
     
     
         4 . The semiconductor device package of  claim 1 , wherein the first conductive layer is patterned to form one or more patterned portions, wherein the patterned portions serve as electrical circuit elements formed in at least one of the lower or upper metallization layers. 
     
     
         5 . The semiconductor device package of  claim 4 ,
 wherein a patterned portion of the first conductive layer forms a resistor in the upper metallization layer, and wherein a stack including a dielectric layer portion and a top conductive layer portion is formed on the resistor,   wherein the dielectric layer portion is formed of the same material and has the same thickness as the dielectric layer of the MIMCAP, and   wherein the top conductive layer portion is formed of the same material and has the same thickness as the second conductive layer of the MIMCAP.   
     
     
         6 . The semiconductor device package of  claim 1 , wherein the second conductive layer is surrounded in a plane of the second conductive layer by a ring structure formed of the same material and having the same thickness as the second conductive layer. 
     
     
         7 . The semiconductor device package of  claim 1 , wherein the lower and upper metallization layers form a power supply layer and a ground layer, respectively, of the interposer substrate. 
     
     
         8 . The semiconductor device package of  claim 1 , wherein at least one of the bottom plate and the top plate is provided with perforations formed therethrough, wherein the perforations are at least partially filled with a dielectric material.