Memory string and semiconductor device including the same

Abstract

A memory string includes a pass transistor, first memory cells connected in series to a drain terminal of the pass transistor, and first to k th memory cell groups connected in parallel to a source terminal of the pass transistor and each including a plurality of second memory cells connected in series. Here, ‘k’ denotes an integer that is equal to or greater than ‘ 2’.

1 - 7 . (canceled) 
     
     
         8 . A semiconductor device comprising:
 first and second memory strings each comprising:
 a pass transistor;
 drain-side memory cells connected in series to a drain terminal of the pass transistor; and 
 
   first and second source-side memory groups connected in parallel to a source terminal of the pass transistor and each including a plurality of source-side memory cells connected in series.   
     
     
         9 . The semiconductor device of  claim 8 , further comprising:
 first source lines connected to and suitable for driving the first source-side memory groups, respectively; and   second source lines connected to and suitable for driving the second source-side memory groups, respectively.   
     
     
         10 . The semiconductor device of  claim 8 , further comprising:
 a first source line suitable for driving the second source-side memory group of the first memory string and the first source-side memory group of the second memory string; and   second source lines suitable for driving the first source-side memory group of the first memory string and the second source-side memory group of the second memory string, respectively.   
     
     
         11 . The semiconductor device of  claim 8 , further comprising:
 a first bit line suitable for driving the drain-side memory cells of the first memory string; and   a second bit line suitable for driving the drain-side memory cells of the second memory string.   
     
     
         12 . The semiconductor device of  claim 8 , further comprising a third memory string configured as the same as the first and second memory strings,
 wherein the source line comprises:   a first source line suitable for driving the second source-side memory group of the first memory string and the first source-side memory group of the second memory string;   a second source line suitable for driving the second source-side memory group of the second memory string and a first source-side memory group of the third memory string; and   third source lines suitable for driving the first source-side memory group of the first memory string and a second source-side memory group of the third memory string, respectively.   
     
     
         13 . The semiconductor device of  claim 12 , further comprising:
 a first bit line suitable for driving drain-side memory cells of the first and third memory strings; and   a second bit line suitable for driving the drain-side memory cells of the second memory string.   
     
     
         14 . A semiconductor device comprising:
 a first channel layer comprising:
 a first pipe channel layer; and 
 a first source-side channel layer, a first drain-side channel layer, and a second source-side channel layer connected to the first pipe channel layer, and arranged in a first direction; 
   first source-side gates stacked and surrounding the first source-side channel layer;   second source-side gates stacked and surrounding the second source-side channel layer; and   first drain-side gates stacked and surrounding the first drain-side channel layer,   wherein the first source-side gates, the second source-side gates, and the first drain-side gates are separated from one another.   
     
     
         15 . The semiconductor device of  claim 14 , further comprising:
 a second channel layer arranged adjacent to the first channel layer in the first direction, and including a second pipe channel layer, and a third source-side channel layer, a second drain-side channel layer, and a fourth source-side channel layer connected to the second pipe channel layer and arranged in the first direction.   
     
     
         16 . The semiconductor device of  claim 15 , further comprising:
 first to fourth source lines connected to the first to fourth source-side channel layers, respectively; and   first and second bit lines connected to the first and second drain-side channel layer, respectively.   
     
     
         17 . The semiconductor device of  claim 15 , wherein the second source-side channel layer and the third source-side channel layer are connected to a same source line, and
 the first drain-side channel layer and the second drain-side channel layer are connected to different bit lines.   
     
     
         18 . The semiconductor device of  claim 14 , further comprising:
 a second channel layer arranged adjacent to the first channel layer in a second direction crossing the first direction, and including a second pipe channel layer, and a third source-side channel layer, a second drain-side channel layer, and a fourth source-side channel layer connected to the second pipe channel layer and arranged in the first direction.   
     
     
         19 . The semiconductor device of  claim 18 , further comprising:
 a first source line connected to the first and third source-side channel layers;   a second source lines connected to the second and fourth source-side channel layers; and   first and second bit lines connected to the first and second drain-side channel layers, respectively,   wherein the first channel layer and the second channel layer are arranged in the second direction to have a center axis oblique to the second direction.   
     
     
         20 . The semiconductor device of  claim 14 , wherein the first channel layer further comprises:
 a third source-side channel layer connected to the first pipe channel layer and disposed between the first source-side channel layer and the first drain-side channel layer; and   a fourth source-side channel layer connected to the first pipe channel layer and disposed between the second source-side channel layer and the first drain-side channel layer,   wherein the semiconductor device includes memory blocks each having the first channel layer in the first direction.