Implementing block device extent granularity authorization model processing in capi adapters

Abstract

A method, system and computer program product are provided for implementing block extent granularity authorization model processing in Coherent Accelerator Processor Interface (CAPI) adapters. The CAPI adapter includes an authorization table and a file system authorization function to authenticate data access for a client at an extent granularity and to prevent an application from accessing unauthorized data in the CAPI adapter. Each authorization table entry provides for the CAPI client, a CAPI client identification (ID), a CAPI server register space assigning resource ownership to the CAPI client with a CAPI set of allowed functions.

1 - 9 . (canceled) 
     
     
         10 . A main memory system for implementing enhanced security in a memory subsystem including Dynamic Random Access Memory (DRAM) in a computer system comprising:
 a main memory;   a memory controller coupled to said main memory,   said memory subsystem coupled to said memory controller;   said memory controller identifying an Error Checking Code (ECC) strength for data by decreasing ECC strength in proportion to an importance value for data;   said memory subsystem comprising a register to hold scrambling information transmitted from a memory controller; and scrambling circuitry on the memory subsystem to scramble at least one of bank select bits and data bits responsive to the scrambling information in the register.   
     
     
         11 . The system as recited in  claim 10  includes control code stored on a computer readable medium, and wherein said memory controller uses said control code to transmit the scrambling information to said memory subsystem. 
     
     
         12 . The system as recited in  claim 10  wherein mainline read and write operations of said memory controller remains unchanged. 
     
     
         13 . The system as recited in  claim 10  wherein the data bits further comprise ECC (Error Checking and Correcting) bits generated with the identified ECC strength. 
     
     
         14 . The system as recited in  claim 10  includes said memory subsystem receiving the normal mainline write from said memory controller, translating and storing write data using the scrambling information. 
     
     
         15 . The system as recited in  claim 10  includes said memory subsystem receiving the normal mainline read from the memory controller includes translating back read data using the scrambling information before sending the read data to the memory controller. 
     
     
         16 . The system as recited in  claim 10  wherein said register to hold scrambling information includes a volatile register to hold the scrambling information only when power is active 
     
     
         17 . The system as recited in  claim 10  wherein said register storing default settings responsive to the power going off and returns active. 
     
     
         18 . The system as recited in  claim 17  wherein said default settings includes traditional one to one mapping of bank select bits and data bits. 
     
     
         19 . The system as recited in  claim 10  wherein said memory controller provides a security level proportional to a level of data rearrangement determined by the scrambling information. 
     
     
         20 . The system as recited in  claim 19  includes said level of data rearrangement programmed by a user.