Resistive memory device and fabrication method thereof

Abstract

A semiconductor integrated circuit device and a fabrication method thereof are disclosed. The resistive memory device includes a lower electrode, a resistive layer formed in a resistance change region on the lower electrode, an upper electrode formed on the resistive layer, and an insertion layer configured to allow a reset current path of the resistive layer, which is formed from the upper electrode to the lower electrode, to be bypassed in a direction perpendicular to or parallel to a surface of the lower electrode.

What is claimed is: 
     
         1 . A semiconductor integrated circuit device comprising:
 a resistive layer serving as a primary current path; and   an insertion layer serving as a bypass current path in a reset mode,   wherein the insertion layer has a resistance value smaller than that of the resistive layer in an amorphous state and greater than that of the resistive layer in a crystalline state.   
     
     
         2 . The semiconductor integrated circuit device of  claim 1 , wherein the insertion layer is formed in the resistive layer and extends in a direction perpendicular to an upper surface of the resistive layer. 
     
     
         3 . The semiconductor integrated circuit device of  claim 2 , wherein a depth of the insertion layer is smaller than a thickness of the resistive layer when measured from the upper surface of the resistive layer. 
     
     
         4 . The semiconductor integrated circuit device of  claim 2 , wherein the insertion layer passes through the resistive layer. 
     
     
         5 . The semiconductor integrated circuit device of  claim 1 , wherein the insertion layer surrounds the resistive layer. 
     
     
         6 . The semiconductor integrated circuit device of  claim 1 , wherein the insertion layer is formed in the resistive layer and extends in a direction substantially parallel to an upper surface of the resistive layer. 
     
     
         7 . The semiconductor integrated circuit device of  claim 1 , wherein the bypass current path includes a vertical path extending in a direction perpendicular to an upper surface of the resistive layer, a horizon path extending in a direction parallel to the upper surface of the resistive layer, or both. 
     
     
         8 . The semiconductor integrated circuit device of  claim 7 , wherein the insertion layer includes:
 a vertical insertion layer formed in a ring shape and surrounded by the resistive layer; and   a horizontal insertion layer extending from a first inner sidewall of the vertical resistive layer to a second inner sidewall of the vertical resistive layer.   
     
     
         9 . The semiconductor integrated circuit device of  claim 8 , wherein a thickness of the horizontal insertion layer is greater than a width of the vertical insertion layer. 
     
     
         10 . The semiconductor integrated circuit device of  claim 8 , wherein a resistance value of the horizontal insertion layer is smaller than that of the vertical insertion layer. 
     
     
         11 . The semiconductor integrated circuit device of  claim 1 , further comprising:
 a lower electrode provided under the resistive layer and the insertion layer.   
     
     
         12 . The semiconductor integrated circuit device of  claim 11 , further comprising:
 an upper electrode provided over the resistive layer and the insertion layer.   
     
     
         13 . A semiconductor integrated circuit device comprising:
 a lower electrode;   a resistive layer formed over the lower electrode and serving as a primary current path;   an upper electrode formed over the resistive layer; and   an insertion layer serving as a bypass current path between the upper electrode and the lower electrode,   wherein the insertion layer includes a vertical insertion layer extending in a direction perpendicular to an upper surface of the lower electrode, a horizontal insertion layer extending in a direction parallel to the upper surface of the lower electrode, or both.   
     
     
         14 . The semiconductor integrated circuit device of  claim 13 , wherein the insertion layer is formed in the resistive layer and extends in the direction perpendicular to the upper surface of the resistive layer. 
     
     
         15 . The semiconductor integrated circuit device of  claim 14 , wherein a depth of the insertion layer is smaller than a thickness of the resistive layer when measured from the upper surface of the resistive layer. 
     
     
         16 . The semiconductor integrated circuit device of  claim 14 , wherein the insertion layer passes through the resistive layer. 
     
     
         17 . The semiconductor integrated circuit device of  claim 13 , wherein the insertion layer surrounds the resistive layer. 
     
     
         18 . The semiconductor integrated circuit device of  claim 13 , wherein the insertion layer is formed in the resistive layer and extends in the direction substantially parallel to the upper surface of the resistive layer. 
     
     
         19 . The semiconductor integrated circuit device of  claim 13 , wherein the insertion layer includes:
 a vertical insertion layer formed in a ring shape and surrounded by the resistive layer; and   a horizontal insertion layer extending from a first inner sidewall of the vertical resistive layer to a second inner sidewall of the vertical resistive layer.   
     
     
         20 . The semiconductor integrated circuit device of  claim 19 , wherein a thickness of the horizontal insertion layer is greater than a width of the vertical insertion layer. 
     
     
         21 . The semiconductor integrated circuit device of  claim 19 , wherein a resistance value of the horizontal insertion layer is smaller than that of the vertical insertion layer. 
     
     
         22 . A method of fabricating a semiconductor integrated circuit device, the method comprising:
 forming a lower electrode;   forming a variable resistor structure including an insertion layer over the lower electrode; and   forming an upper electrode over the variable resistor structure,   wherein the insertion layer forms a bypass current path in a reset mode, and   wherein the bypass current path extends in a direction perpendicular to an upper surface of the lower electrode, in a direction parallel to the upper surface of the lower electrode, or both.   
     
     
         23 . The method of  claim 22 , wherein the forming of the variable resistor structure includes:
 forming a resistive layer over the lower electrode;   forming a hole in the resistive layer; and   forming the insertion layer in the hole.   
     
     
         24 . The method of  claim 22 , wherein the forming of the variable resistor structure includes:
 alternately stacking an insulating layer and a horizontal insertion layer over the lower electrode to form a stack;   forming a preliminary resistor structure by etching the stack;   forming a vertical insertion layer surrounding the preliminary resistor structure; and   forming a resistive layer surrounding the vertical insertion layer.   
     
     
         25 . The method of  claim 22 , further comprising:
 forming an interlayer insulating layer between the variable resistor structure and an adjacent variable resistor structure,   wherein the forming of the interlayer insulating layer is performed between the forming of the variable resistor structure and the forming of the upper electrode.