Semiconductor device having a gate and a conductive line in a pillar pattern

Abstract

A semiconductor device including a vertical gate and a method for manufacturing the same are disclosed, which prevent a floating body phenomenon, thereby increasing a cell threshold voltage and reducing leakage current, resulting in improved refresh properties of the semiconductor device. The semiconductor device includes a plurality of pillar patterns, including first pillar patterns arranged along a first direction and second pillar patterns arranged along a second direction, formed over a semiconductor substrate; a gate extending in the first direction, arranged along sidewalls of the first pillar patterns, and configured to couple the first pillar patterns; a junction region formed in an upper portion of the pillar patterns; and a conductive line arranged along the sidewalls of the first pillar patterns and provided in a region disposed below the junction region and over the gate.

1 - 9 . (canceled) 
     
     
         10 . A method for manufacturing a semiconductor device, comprising:
 forming a plurality of pillar patterns, including first pillar patterns arranged along a first direction and second pillar patterns arranged along a second direction, by etching a semiconductor substrate;   forming a gate extending in the first direction, disposed over sidewalls of the first pillar patterns, and configured to couple the first pillar patterns;   forming a conductive line disposed over the gate and arranged along the sidewalls of the first pillar patterns; and   forming a first junction region in an upper portion of the pillar patterns, a lower surface of the first junction region being disposed at a higher level than an upper surface of the conductive line.   
     
     
         11 . The method according to  claim 10 , the method further comprising:
 forming a bit line conductive material over the semiconductor substrate including the pillar patterns; and   etching the bit line conductive material to form a bit line in a lower region between the first pillar patterns, the bit line extending in the second direction,   wherein the first direction is perpendicular to the second direction.   
     
     
         12 . The method according to  claim 11 , the method further comprising forming a first insulating film over a portion of the semiconductor substrate disposed between the first pillar patterns and disposed over the bit line. 
     
     
         13 . The method according to  claim 12 , wherein forming the gate includes:
 forming a gate conductive material over the first insulating film between the first pillar patterns;   forming a spacer over the gate conductive material at an upper portion of the sidewalls of the first pillar patterns; and   etching the gate conductive material using the spacer as an etch mask.   
     
     
         14 . The method according to  claim 13 , the method further comprising:
 forming a gate insulating film over the sidewalls of the first pillar patterns before forming the gate conductive material.   
     
     
         15 . The method according to  claim 12 , the method further comprising:
 forming a second insulating film over the portion of the semiconductor substrate disposed between the first pillar patterns and over the gate.   
     
     
         16 . The method according to  claim 15 , wherein forming the conductive line includes:
 forming a polysilicon layer over the pillar patterns and the second insulating film; and   etching the polysilicon layer so that the polysilicon layer remains at a predetermined thickness over the insulating film.   
     
     
         17 . The method according to  claim 16 , wherein the polysilicon layer is a p-type polysilicon layer. 
     
     
         18 . The method according to  claim 10 , the method further comprising:
 forming a second junction region in a portion of the pillar patterns coupled to the conductive line by implementing a thermal treatment process.   
     
     
         19 . The method according to  claim 10 , wherein forming the first junction region includes implanting n-type ions into an upper surface of the pillar patterns. 
     
     
         20 . The method according to  claim 10 , further comprising forming a storage node over the pillar patterns after forming the first junction region, the storage node being coupled to the first junction region.